arm64: dts: qcom: msm8939: fixup a53pll nodes

Signed-off-by: Fabien Parent <fabien.parent@linaro.org>

1 files changed, 142 insertions, 1 deletions

diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi
index effc13080bd6..cc6c1dd0af6d 100644
--- a/arch/arm64/boot/dts/qcom/msm8939.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi
@@ -2107,6 +2107,113 @@
 			compatible = "qcom,msm8939-a53pll";
 			reg = <0x0b016000 0x40>;
 			#clock-cells = <0>;
+			clocks = <&xo_board>;
+			clock-names = "xo";
+			operating-points-v2 = <&a53pll_c1_opp_table>;
+
+			a53pll_c1_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-652800000 {
+					opp-hz = /bits/ 64 <652800000>;
+				};
+
+				opp-691200000 {
+					opp-hz = /bits/ 64 <691200000>;
+				};
+
+				opp-729600000 {
+					opp-hz = /bits/ 64 <729600000>;
+				};
+
+				opp-806400000 {
+					opp-hz = /bits/ 64 <806400000>;
+				};
+
+				opp-844800000 {
+					opp-hz = /bits/ 64 <844800000>;
+				};
+
+				opp-883200000 {
+					opp-hz = /bits/ 64 <883200000>;
+				};
+
+				opp-960000000 {
+					opp-hz = /bits/ 64 <960000000>;
+				};
+
+				opp-998400000 {
+					opp-hz = /bits/ 64 <998400000>;
+				};
+
+				opp-1036800000 {
+					opp-hz = /bits/ 64 <1036800000>;
+				};
+
+				opp-1113600000 {
+					opp-hz = /bits/ 64 <1113600000>;
+				};
+
+				opp-1209600000 {
+					opp-hz = /bits/ 64 <1209600000>;
+				};
+
+				opp-1190400000 {
+					opp-hz = /bits/ 64 <1190400000>;
+				};
+
+				opp-1267200000 {
+					opp-hz = /bits/ 64 <1267200000>;
+				};
+
+				opp-1344000000 {
+					opp-hz = /bits/ 64 <1344000000>;
+				};
+
+				opp-1363200000 {
+					opp-hz = /bits/ 64 <1363200000>;
+				};
+
+				opp-1420800000 {
+					opp-hz = /bits/ 64 <1420800000>;
+				};
+
+				opp-1459200000 {
+					opp-hz = /bits/ 64 <1459200000>;
+				};
+
+				opp-1497600000 {
+					opp-hz = /bits/ 64 <1497600000>;
+				};
+
+				opp-1536000000 {
+					opp-hz = /bits/ 64 <1536000000>;
+				};
+
+				opp-1574400000 {
+					opp-hz = /bits/ 64 <1574400000>;
+				};
+
+				opp-1612800000 {
+					opp-hz = /bits/ 64 <1612800000>;
+				};
+
+				opp-1632000000 {
+					opp-hz = /bits/ 64 <1632000000>;
+				};
+
+				opp-1651200000 {
+					opp-hz = /bits/ 64 <1651200000>;
+				};
+
+				opp-1689600000 {
+					opp-hz = /bits/ 64 <1689600000>;
+				};
+
+				opp-1708800000 {
+					opp-hz = /bits/ 64 <1708800000>;
+				};
+			};
 		};
 
 		acc0: clock-controller@b088000 {
@@ -2159,9 +2266,28 @@
 		};
 
 		a53pll_c0: clock@b116000 {
-			compatible = "qcom,msm8939-a53pll";
+			compatible = "qcom,msm8939-a53pll-c0";
 			reg = <0x0b116000 0x40>;
 			#clock-cells = <0>;
+			clocks = <&xo_board>;
+			clock-names = "xo";
+			operating-points-v2 = <&a53pll_c0_opp_table>;
+
+			a53pll_c0_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-998400000 {
+					opp-hz = /bits/ 64 <998400000>;
+				};
+
+				opp-1113600000 {
+					opp-hz = /bits/ 64 <1113600000>;
+				};
+
+				opp-1209600000 {
+					opp-hz = /bits/ 64 <1209600000>;
+				};
+			};
 		};
 
 		acc4: clock-controller@b188000 {
@@ -2208,6 +2334,21 @@
 			compatible = "qcom,msm8939-a53pll";
 			reg = <0x0b1d0000 0x40>;
 			#clock-cells = <0>;
+			clocks = <&xo_board>;
+			clock-names = "xo";
+			operating-points-v2 = <&a53pll_cci_opp_table>;
+
+			a53pll_cci_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-403200000 {
+					opp-hz = /bits/ 64 <403200000>;
+				};
+
+				opp-595200000 {
+					opp-hz = /bits/ 64 <595200000>;
+				};
+			};
 		};
 
 		apcs2: mailbox@b1d1000 {