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// SPDX-License-Identifier: GPL-2.0
#ifndef _IPA_REG_NEW_H
#define _IPA_REG_NEW_H
#include "linux.h"
struct ipa_reg {
u32 offset;
u32 field_count;
u32 stride;
const u32 *fmask; /* BIT(nr) or GENMASK(h, l) */
const char *name;
};
struct ipa_regs {
u32 reg_count;
const struct ipa_reg **reg;
};
enum ipa_reg_name {
IPA_REG_COMP_CFG,
IPA_REG_CLKON_CFG,
IPA_REG_ROUTE,
IPA_REG_SHARED_MEM_SIZE,
};
#define IPA_REG(__NAME, __name, __offset) \
IPA_REG_STRIDE(__NAME, __name, __offset, 0)
#define IPA_REG_STRIDE(__NAME, __name, __offset, __stride) \
static const struct ipa_reg ipa_reg_ ## __name = { \
.name = #__NAME, \
.offset = __offset, \
.stride = __stride, \
}
#define IPA_REG_FIELDS(__NAME, __name, __offset) \
IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, 0)
#define IPA_REG_STRIDE_FIELDS(__NAME, __name, __offset, __stride) \
static const struct ipa_reg ipa_reg_ ## __name = { \
.name = #__NAME, \
.offset = __offset, \
.stride = __stride, \
.field_count = ARRAY_SIZE(ipa_reg_ ## __name ## _field), \
.fmask = ipa_reg_ ## __name ## _field, \
}
enum ipa_reg_comp_cfg_field_name {
COMP_CFG_ENABLE, /* Not IPA v4.0+ */
RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS, /* IPA v4.7+ */
COMP_CFG_GSI_SNOC_BYPASS_DIS,
COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS,
COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS,
COMP_CFG_IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */
COMP_CFG_IPA_QMB_SELECT_CONS_EN, /* IPA v4.0+ */
COMP_CFG_IPA_QMB_SELECT_PROD_EN, /* IPA v4.0+ */
COMP_CFG_GSI_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
COMP_CFG_GSI_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS, /* IPA v4.0+ */
COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS, /* IPA v4.0+ */
COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS, /* IPA v4.0+ */
COMP_CFG_GSI_SNOC_CNOC_LOOP_PROT_DISABLE, /* IPA v4.0+ */
COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS, /* IPA v4.0+ */
COMP_CFG_IPA_QMB_SELECT_GLOBAL_EN, /* IPA v4.0+ */
COMP_CFG_QMB_RAM_RD_CACHE_DISABLE, /* IPA v4.9+ */
COMP_CFG_GENQMB_AOOOWR, /* IPA v4.9+ */
COMP_CFG_IF_OUT_OF_BUF_STOP_RESET_MASK_EN, /* IPA v4.9+ */
COMP_CFG_GEN_QMB_1_DYNAMIC_ASIZE, /* IPA v4.9+ */
COMP_CFG_GEN_QMB_0_DYNAMIC_ASIZE, /* IPA v4.9+ */
COMP_CFG_ATOMIC_FETCHER_ARB_LOCK_DIS, /* IPA v4.0+ */
COMP_CFG_FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */
};
enum ipa_reg_clkon_cfg_field_name {
CLKON_CFG_RX,
CLKON_CFG_PROC,
CLKON_CFG_TX_WRAPPER,
CLKON_CFG_MISC,
CLKON_CFG_RAM_ARB,
CLKON_CFG_FTCH_HPS,
CLKON_CFG_FTCH_DPS,
CLKON_CFG_HPS,
CLKON_CFG_DPS,
CLKON_CFG_RX_HPS_CMDQS,
CLKON_CFG_HPS_DPS_CMDQS,
CLKON_CFG_DPS_TX_CMDQS,
CLKON_CFG_RSRC_MNGR,
CLKON_CFG_CTX_HANDLER,
CLKON_CFG_ACK_MNGR,
CLKON_CFG_D_DCPH,
CLKON_CFG_H_DCPH,
CLKON_CFG_DCMP, /* Not IPA v4.5+ */
CLKON_CFG_NTF_TX_CMDQS, /* IPA v3.5+ */
CLKON_CFG_TX_0, /* IPA v3.5+ */
CLKON_CFG_TX_1, /* IPA v3.5+ */
CLKON_CFG_FNR, /* IPA v3.5.1+ */
CLKON_CFG_QSB2AXI_CMDQ_L, /* IPA v4.0+ */
CLKON_CFG_AGGR_WRAPPER, /* IPA v4.0+ */
CLKON_CFG_RAM_SLAVEWAY, /* IPA v4.0+ */
CLKON_CFG_QMB, /* IPA v4.0+ */
CLKON_CFG_WEIGHT_ARB, /* IPA v4.0+ */
CLKON_CFG_GSI_IF, /* IPA v4.0+ */
CLKON_CFG_GLOBAL, /* IPA v4.0+ */
CLKON_CFG_GLOBAL_2X_CLK, /* IPA v4.0+ */
CLKON_CFG_DPL_FIFO, /* IPA v4.5+ */
CLKON_CFG_DRBIP, /* IPA v4.7+ */
};
enum ipa_reg_route_field_name {
ROUTE_DIS,
ROUTE_DEF_PIPE,
ROUTE_DEF_HDR_TABLE,
ROUTE_DEF_HDR_OFST,
ROUTE_FRAG_DEF_PIPE,
ROUTE_DEF_RETAIN_HDR,
};
enum ipa_reg_shared_mem_size_field_name {
SHARED_MEM_SIZE,
SHARED_MEM_BADDR,
};
extern const struct ipa_regs ipa_regs_v3_0;
extern const struct ipa_regs ipa_regs_v3_1;
extern const struct ipa_regs ipa_regs_v3_5;
extern const struct ipa_regs ipa_regs_v3_5_1;
extern const struct ipa_regs ipa_regs_v4_0;
extern const struct ipa_regs ipa_regs_v4_1;
extern const struct ipa_regs ipa_regs_v4_2;
extern const struct ipa_regs ipa_regs_v4_5;
extern const struct ipa_regs ipa_regs_v4_7;
extern const struct ipa_regs ipa_regs_v4_9;
extern const struct ipa_regs ipa_regs_v4_11;
#endif /* _IPA_REG_NEW_H */
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