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// SPDX-License-Identifier: GPL-2.0
#include "linux.h"
#include "ipa_reg_new.h"
static const u32 ipa_reg_comp_cfg_field[] = {
/* Bit 0 reserved */
[COMP_CFG_GSI_SNOC_BYPASS_DIS] = BIT(1),
[COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
/* Bit 4 reserved */
[COMP_CFG_IPA_QMB_SELECT_CONS_EN] = BIT(5),
[COMP_CFG_IPA_QMB_SELECT_PROD_EN] = BIT(6),
[COMP_CFG_GSI_MULTI_INORDER_RD_DIS] = BIT(7),
[COMP_CFG_GSI_MULTI_INORDER_WR_DIS] = BIT(8),
[COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9),
[COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10),
[COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11),
[COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12),
[COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13),
[COMP_CFG_GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14),
[COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS] = BIT(15),
[COMP_CFG_IPA_QMB_SELECT_GLOBAL_EN] = BIT(16),
[COMP_CFG_ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17),
[COMP_CFG_FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21),
/* Bits 22-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_clkon_cfg_field[] = {
[CLKON_CFG_RX] = BIT(0),
[CLKON_CFG_PROC] = BIT(1),
[CLKON_CFG_TX_WRAPPER] = BIT(2),
[CLKON_CFG_MISC] = BIT(3),
[CLKON_CFG_RAM_ARB] = BIT(4),
[CLKON_CFG_FTCH_HPS] = BIT(5),
[CLKON_CFG_FTCH_DPS] = BIT(6),
[CLKON_CFG_HPS] = BIT(7),
[CLKON_CFG_DPS] = BIT(8),
[CLKON_CFG_RX_HPS_CMDQS] = BIT(9),
[CLKON_CFG_HPS_DPS_CMDQS] = BIT(10),
[CLKON_CFG_DPS_TX_CMDQS] = BIT(11),
[CLKON_CFG_RSRC_MNGR] = BIT(12),
[CLKON_CFG_CTX_HANDLER] = BIT(13),
[CLKON_CFG_ACK_MNGR] = BIT(14),
[CLKON_CFG_D_DCPH] = BIT(15),
[CLKON_CFG_H_DCPH] = BIT(16),
/* Bit 17 reserved */
[CLKON_CFG_NTF_TX_CMDQS] = BIT(18),
[CLKON_CFG_TX_0] = BIT(19),
[CLKON_CFG_TX_1] = BIT(20),
[CLKON_CFG_FNR] = BIT(21),
[CLKON_CFG_QSB2AXI_CMDQ_L] = BIT(22),
[CLKON_CFG_AGGR_WRAPPER] = BIT(23),
[CLKON_CFG_RAM_SLAVEWAY] = BIT(24),
[CLKON_CFG_QMB] = BIT(25),
[CLKON_CFG_WEIGHT_ARB] = BIT(26),
[CLKON_CFG_GSI_IF] = BIT(27),
[CLKON_CFG_GLOBAL] = BIT(28),
[CLKON_CFG_GLOBAL_2X_CLK] = BIT(29),
[CLKON_CFG_DPL_FIFO] = BIT(30),
/* Bit 31 reserved */
};
IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 ipa_reg_route_field[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
/* Bits 22-23 reserved */
[ROUTE_DEF_RETAIN_HDR] = BIT(24),
/* Bits 25-31 reserved */
};
IPA_REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 ipa_reg_shared_mem_size_field[] = {
[SHARED_MEM_SIZE] = GENMASK(15, 0),
[SHARED_MEM_BADDR] = GENMASK(31, 16),
};
IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const struct ipa_reg *ipa_reg[] = {
[IPA_REG_COMP_CFG] = &ipa_reg_comp_cfg,
[IPA_REG_CLKON_CFG] = &ipa_reg_clkon_cfg,
[IPA_REG_ROUTE] = &ipa_reg_route,
[IPA_REG_SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size,
};
const struct ipa_regs ipa_regs_v4_5 = {
.reg_count = ARRAY_SIZE(ipa_reg),
.reg = ipa_reg,
};
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