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// SPDX-License-Identifier: GPL-2.0
#include "linux.h"
#include "ipa_reg_new.h"
static const u32 ipa_reg_comp_cfg_field[] = {
[COMP_CFG_ENABLE] = BIT(0),
[COMP_CFG_GSI_SNOC_BYPASS_DIS] = BIT(1),
[COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2),
[COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3),
[COMP_CFG_IPA_DCMP_FAST_CLK_EN] = BIT(4),
/* Bits 5-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
static const u32 ipa_reg_clkon_cfg_field[] = {
[CLKON_CFG_RX] = BIT(0),
[CLKON_CFG_PROC] = BIT(1),
[CLKON_CFG_TX_WRAPPER] = BIT(2),
[CLKON_CFG_MISC] = BIT(3),
[CLKON_CFG_RAM_ARB] = BIT(4),
[CLKON_CFG_FTCH_HPS] = BIT(5),
[CLKON_CFG_FTCH_DPS] = BIT(6),
[CLKON_CFG_HPS] = BIT(7),
[CLKON_CFG_DPS] = BIT(8),
[CLKON_CFG_RX_HPS_CMDQS] = BIT(9),
[CLKON_CFG_HPS_DPS_CMDQS] = BIT(10),
[CLKON_CFG_DPS_TX_CMDQS] = BIT(11),
[CLKON_CFG_RSRC_MNGR] = BIT(12),
[CLKON_CFG_CTX_HANDLER] = BIT(13),
[CLKON_CFG_ACK_MNGR] = BIT(14),
[CLKON_CFG_D_DCPH] = BIT(15),
[CLKON_CFG_H_DCPH] = BIT(16),
[CLKON_CFG_DCMP] = BIT(17),
/* Bits 18-31 reserved */
};
IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
static const u32 ipa_reg_route_field[] = {
[ROUTE_DIS] = BIT(0),
[ROUTE_DEF_PIPE] = GENMASK(5, 1),
[ROUTE_DEF_HDR_TABLE] = BIT(6),
[ROUTE_DEF_HDR_OFST] = GENMASK(16, 7),
[ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17),
/* Bits 22-23 reserved */
[ROUTE_DEF_RETAIN_HDR] = BIT(24),
/* Bits 25-31 reserved */
};
IPA_REG_FIELDS(ROUTE, route, 0x00000048);
static const u32 ipa_reg_shared_mem_size_field[] = {
[SHARED_MEM_SIZE] = GENMASK(15, 0),
[SHARED_MEM_BADDR] = GENMASK(31, 16),
};
IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
static const u32 ipa_reg_qsb_max_writes_field[] = {
[GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
[GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
static const u32 ipa_reg_qsb_max_reads_field[] = {
[GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
[GEN_QMB_1_MAX_READS] = GENMASK(7, 4),
/* Bits 8-31 reserved */
};
IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
static const u32 ipa_reg_filt_rout_hash_en_field[] = {
[IPV6_ROUTER_HASH] = GENMASK(0, 0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = GENMASK(4, 4),
/* Bits 5-7 reserved */
[IPV4_ROUTER_HASH] = GENMASK(8, 8),
/* Bits 9-11 reserved */
[IPV4_FILTER_HASH] = GENMASK(12, 12),
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000008c);
static const u32 ipa_reg_filt_rout_hash_flush_field[] = {
[IPV6_ROUTER_HASH] = GENMASK(0, 0),
/* Bits 1-3 reserved */
[IPV6_FILTER_HASH] = GENMASK(4, 4),
/* Bits 5-7 reserved */
[IPV4_ROUTER_HASH] = GENMASK(8, 8),
/* Bits 9-11 reserved */
[IPV4_FILTER_HASH] = GENMASK(12, 12),
/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x00000090);
/* ipa->available defines valid bits (no fields) */
IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c);
static const u32 ipa_reg_bcr_field[] = {
[BCR_CMDQ_L_LACK_ONE_ENTRY] = BIT(0),
[BCR_TX_NOT_USING_BRESP] = BIT(1),
[BCR_TX_SUSPEND_IRQ_ASSERT_ONCE] = BIT(2),
[BCR_SUSPEND_L2_IRQ] = BIT(3),
[BCR_HOLB_DROP_L2_IRQ] = BIT(4),
/* Bits 5-31 reserved */
};
IPA_REG_FIELDS(BCR, bcr, 0x000001d0);
static const u32 ipa_reg_local_pkt_proc_cntxt_field[] = {
[LOCAL_PKT_CNTXT_BASE_ADDR] = GENMASK(16, 0),
/* Bits 17-31 reserved */
};
/* Offset must be a multiple of 8 (bottom 3 bits 0) */
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
/* ipa->available defines valid bits (no fields) */
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);
static const u32 ipa_reg_counter_cfg_field[] = {
[EOT_COAL_GRANULARITY] = GENMASK(3, 0),
[AGGR_GRANULARITY] = GENMASK(8, 4),
/* Bits 9-31 reserved */
};
IPA_REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0);
static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_n_field[] = {
[RSRC_GRP_X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[RSRC_GRP_X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[RSRC_GRP_Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[RSRC_GRP_Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE_N, src_rsrc_grp_01_rsrc_type_n,
0x00000400, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_n_field[] = {
[RSRC_GRP_X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[RSRC_GRP_X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[RSRC_GRP_Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[RSRC_GRP_Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE_N, src_rsrc_grp_23_rsrc_type_n,
0x00000404, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_n_field[] = {
[RSRC_GRP_X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[RSRC_GRP_X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[RSRC_GRP_Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[RSRC_GRP_Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE_N, src_rsrc_grp_45_rsrc_type_n,
0x00000408, 0x0020);
static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_n_field[] = {
[RSRC_GRP_X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[RSRC_GRP_X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[RSRC_GRP_Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[RSRC_GRP_Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE_N, src_rsrc_grp_67_rsrc_type_n,
0x0000040c, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_n_field[] = {
[RSRC_GRP_X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[RSRC_GRP_X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[RSRC_GRP_Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[RSRC_GRP_Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE_N, dst_rsrc_grp_01_rsrc_type_n,
0x00000500, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_n_field[] = {
[RSRC_GRP_X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[RSRC_GRP_X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[RSRC_GRP_Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[RSRC_GRP_Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE_N, dst_rsrc_grp_23_rsrc_type_n,
0x00000504, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_n_field[] = {
[RSRC_GRP_X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[RSRC_GRP_X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[RSRC_GRP_Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[RSRC_GRP_Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE_N, dst_rsrc_grp_45_rsrc_type_n,
0x00000508, 0x0020);
static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_n_field[] = {
[RSRC_GRP_X_MIN_LIM] = GENMASK(5, 0),
/* Bits 6-7 reserved */
[RSRC_GRP_X_MAX_LIM] = GENMASK(13, 8),
/* Bits 14-15 reserved */
[RSRC_GRP_Y_MIN_LIM] = GENMASK(21, 16),
/* Bits 22-23 reserved */
[RSRC_GRP_Y_MAX_LIM] = GENMASK(29, 24),
/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE_N, dst_rsrc_grp_67_rsrc_type_n,
0x0000050c, 0x0020);
static const struct ipa_reg *ipa_reg[] = {
[IPA_REG_COMP_CFG] = &ipa_reg_comp_cfg,
[IPA_REG_CLKON_CFG] = &ipa_reg_clkon_cfg,
[IPA_REG_ROUTE] = &ipa_reg_route,
[IPA_REG_SHARED_MEM_SIZE] = &ipa_reg_shared_mem_size,
[IPA_REG_QSB_MAX_WRITES] = &ipa_reg_qsb_max_writes,
[IPA_REG_QSB_MAX_READS] = &ipa_reg_qsb_max_reads,
[IPA_REG_FILT_ROUT_HASH_EN] = &ipa_reg_filt_rout_hash_en,
[IPA_REG_FILT_ROUT_HASH_FLUSH] = &ipa_reg_filt_rout_hash_flush,
[IPA_REG_STATE_AGGR_ACTIVE] = &ipa_reg_state_aggr_active,
[IPA_REG_BCR] = &ipa_reg_bcr,
[IPA_REG_LOCAL_PKT_PROC_CNTXT] = &ipa_reg_local_pkt_proc_cntxt,
[IPA_REG_AGGR_FORCE_CLOSE] = &ipa_reg_aggr_force_close,
[IPA_REG_COUNTER_CFG] = &ipa_reg_counter_cfg,
[IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N] =
&ipa_reg_src_rsrc_grp_01_rsrc_type_n,
[IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N] =
&ipa_reg_src_rsrc_grp_23_rsrc_type_n,
[IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N] =
&ipa_reg_src_rsrc_grp_45_rsrc_type_n,
[IPA_REG_SRC_RSRC_GRP_67_RSRC_TYPE_N] =
&ipa_reg_src_rsrc_grp_67_rsrc_type_n,
[IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N] =
&ipa_reg_dst_rsrc_grp_01_rsrc_type_n,
[IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N] =
&ipa_reg_dst_rsrc_grp_23_rsrc_type_n,
[IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N] =
&ipa_reg_dst_rsrc_grp_45_rsrc_type_n,
[IPA_REG_DST_RSRC_GRP_67_RSRC_TYPE_N] =
&ipa_reg_dst_rsrc_grp_67_rsrc_type_n,
};
const struct ipa_regs ipa_regs_v3_1 = {
.reg_count = ARRAY_SIZE(ipa_reg),
.reg = ipa_reg,
};
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