// SPDX-License-Identifier: GPL-2.0

#include "linux.h"
#include "ipa_reg_new.h"

static const u32 ipa_reg_comp_cfg_field[] = {
	/* Bit 0 reserved */
	[COMP_CFG_GSI_SNOC_BYPASS_DIS]			= BIT(1),
	[COMP_CFG_GEN_QMB_0_SNOC_BYPASS_DIS]		= BIT(2),
	[COMP_CFG_GEN_QMB_1_SNOC_BYPASS_DIS]		= BIT(3),
	/* Bit 4 reserved */
	[COMP_CFG_IPA_QMB_SELECT_CONS_EN]		= BIT(5),
	[COMP_CFG_IPA_QMB_SELECT_PROD_EN]		= BIT(6),
	[COMP_CFG_GSI_MULTI_INORDER_RD_DIS]		= BIT(7),
	[COMP_CFG_GSI_MULTI_INORDER_WR_DIS]		= BIT(8),
	[COMP_CFG_GEN_QMB_0_MULTI_INORDER_RD_DIS]	= BIT(9),
	[COMP_CFG_GEN_QMB_1_MULTI_INORDER_RD_DIS]	= BIT(10),
	[COMP_CFG_GEN_QMB_0_MULTI_INORDER_WR_DIS]	= BIT(11),
	[COMP_CFG_GEN_QMB_1_MULTI_INORDER_WR_DIS]	= BIT(12),
	[COMP_CFG_GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS]	= BIT(13),
	[COMP_CFG_GSI_SNOC_CNOC_LOOP_PROT_DISABLE]	= BIT(14),
	[COMP_CFG_GSI_MULTI_AXI_MASTERS_DIS]		= BIT(15),
	[COMP_CFG_IPA_QMB_SELECT_GLOBAL_EN]		= BIT(16),
	[COMP_CFG_ATOMIC_FETCHER_ARB_LOCK_DIS]		= GENMASK(20, 17),
	[COMP_CFG_FULL_FLUSH_WAIT_RS_CLOSURE_EN]	= BIT(21),
	/* Bits 22-31 reserved */
};
IPA_REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);

static const u32 ipa_reg_clkon_cfg_field[] = {
	[CLKON_CFG_RX]					= BIT(0),
	[CLKON_CFG_PROC]				= BIT(1),
	[CLKON_CFG_TX_WRAPPER]				= BIT(2),
	[CLKON_CFG_MISC]				= BIT(3),
	[CLKON_CFG_RAM_ARB]				= BIT(4),
	[CLKON_CFG_FTCH_HPS]				= BIT(5),
	[CLKON_CFG_FTCH_DPS]				= BIT(6),
	[CLKON_CFG_HPS]					= BIT(7),
	[CLKON_CFG_DPS]					= BIT(8),
	[CLKON_CFG_RX_HPS_CMDQS]			= BIT(9),
	[CLKON_CFG_HPS_DPS_CMDQS]			= BIT(10),
	[CLKON_CFG_DPS_TX_CMDQS]			= BIT(11),
	[CLKON_CFG_RSRC_MNGR]				= BIT(12),
	[CLKON_CFG_CTX_HANDLER]				= BIT(13),
	[CLKON_CFG_ACK_MNGR]				= BIT(14),
	[CLKON_CFG_D_DCPH]				= BIT(15),
	[CLKON_CFG_H_DCPH]				= BIT(16),
	/* Bit 17 reserved */
	[CLKON_CFG_NTF_TX_CMDQS]			= BIT(18),
	[CLKON_CFG_TX_0]				= BIT(19),
	[CLKON_CFG_TX_1]				= BIT(20),
	[CLKON_CFG_FNR]					= BIT(21),
	[CLKON_CFG_QSB2AXI_CMDQ_L]			= BIT(22),
	[CLKON_CFG_AGGR_WRAPPER]			= BIT(23),
	[CLKON_CFG_RAM_SLAVEWAY]			= BIT(24),
	[CLKON_CFG_QMB]					= BIT(25),
	[CLKON_CFG_WEIGHT_ARB]				= BIT(26),
	[CLKON_CFG_GSI_IF]				= BIT(27),
	[CLKON_CFG_GLOBAL]				= BIT(28),
	[CLKON_CFG_GLOBAL_2X_CLK]			= BIT(29),
	[CLKON_CFG_DPL_FIFO]				= BIT(30),
	/* Bit 31 reserved */
};
IPA_REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);

static const u32 ipa_reg_route_field[] = {
	[ROUTE_DIS]					= BIT(0),
	[ROUTE_DEF_PIPE]				= GENMASK(5, 1),
	[ROUTE_DEF_HDR_TABLE]				= BIT(6),
	[ROUTE_DEF_HDR_OFST]				= GENMASK(16, 7),
	[ROUTE_FRAG_DEF_PIPE]				= GENMASK(21, 17),
	/* Bits 22-23 reserved */
	[ROUTE_DEF_RETAIN_HDR]				= BIT(24),
	/* Bits 25-31 reserved */
};
IPA_REG_FIELDS(ROUTE, route, 0x00000048);

static const u32 ipa_reg_shared_mem_size_field[] = {
	[SHARED_MEM_SIZE]				= GENMASK(15, 0),
	[SHARED_MEM_BADDR]				= GENMASK(31, 16),
};
IPA_REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);

static const u32 ipa_reg_qsb_max_writes_field[] = {
	[GEN_QMB_0_MAX_WRITES]				= GENMASK(3, 0),
	[GEN_QMB_1_MAX_WRITES]				= GENMASK(7, 4),
	/* Bits 8-31 reserved */
};
IPA_REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);

static const u32 ipa_reg_qsb_max_reads_field[] = {
	[GEN_QMB_0_MAX_READS]				= GENMASK(3, 0),
	[GEN_QMB_1_MAX_READS]				= GENMASK(7, 4),
	/* Bits 8-15 reserved */
	[GEN_QMB_0_MAX_READS_BEATS]			= GENMASK(23, 16),
	[GEN_QMB_1_MAX_READS_BEATS]			= GENMASK(31, 24),
};
IPA_REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);

static const u32 ipa_reg_filt_rout_hash_en_field[] = {
	[IPV6_ROUTER_HASH]				= GENMASK(0, 0),
	/* Bits 1-3 reserved */
	[IPV6_FILTER_HASH]				= GENMASK(4, 4),
	/* Bits 5-7 reserved */
	[IPV4_ROUTER_HASH]				= GENMASK(8, 8),
	/* Bits 9-11 reserved */
	[IPV4_FILTER_HASH]				= GENMASK(12, 12),
	/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x00000148);

static const u32 ipa_reg_filt_rout_hash_flush_field[] = {
	[IPV6_ROUTER_HASH]				= GENMASK(0, 0),
	/* Bits 1-3 reserved */
	[IPV6_FILTER_HASH]				= GENMASK(4, 4),
	/* Bits 5-7 reserved */
	[IPV4_ROUTER_HASH]				= GENMASK(8, 8),
	/* Bits 9-11 reserved */
	[IPV4_FILTER_HASH]				= GENMASK(12, 12),
	/* Bits 13-31 reserved */
};
IPA_REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000014c);

/* ipa->available defines valid bits (no fields) */
IPA_REG(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4);

static const u32 ipa_reg_local_pkt_proc_cntxt_field[] = {
	[LOCAL_PKT_CNTXT_BASE_ADDR]			= GENMASK(17, 0),
	/* Bits 18-31 reserved */
};
/* Offset must be a multiple of 8 (bottom 3 bits 0) */
IPA_REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);

/* ipa->available defines valid bits (no fields) */
IPA_REG(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec);

static const u32 ipa_reg_tx_cfg_field[] = {
	/* Bits 0-1 reserved */
	[PREFETCH_ALMOST_EMPTY_SIZE_TX0]		= GENMASK(5, 2),
	[DMAW_SCND_OUTSD_PRED_THRESHOLD]		= GENMASK(9, 6),
	[DMAW_SCND_OUTSD_PRED_EN]			= BIT(10),
	[DMAW_MAX_BEATS_256_DIS]			= BIT(11),
	[PA_MASK_EN]					= BIT(12),
	[PREFETCH_ALMOST_EMPTY_SIZE_TX1]		= GENMASK(16, 13),
	[DUAL_TX_ENABLE]				= BIT(17),
	/* Bits 18-31 reserved */
};
IPA_REG_FIELDS(TX_CFG, tx_cfg, 0x000001fc);

static const u32 ipa_reg_flavor_0_field[] = {
	[IPA_MAX_PIPES]					= GENMASK(3, 0),
	/* Bits 4-7 reserved */
	[IPA_MAX_CONS_PIPES]				= GENMASK(12, 8),
	/* Bits 13-19 reserved */
	[IPA_MAX_PROD_PIPES]				= GENMASK(20, 16),
	/* Bits 17-26 reserved */
	[IPA_PROD_LOWEST]				= GENMASK(27, 24),
	/* Bits 28-31 reserved */
};
IPA_REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);

static const u32 ipa_reg_idle_indication_cfg_field[] = {
	[ENTER_IDLE_DEBOUNCE_THRESH]			= GENMASK(15, 0),
	[CONST_NON_IDLE_ENABLE]				= BIT(16),
	/* Bits 17-31 reserved */
};
IPA_REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);

static const u32 ipa_reg_qtime_timestamp_cfg_field[] = {
	[DPL_TIMESTAMP_LSB]				= GENMASK(4, 0),
	/* Bits 5-6 reserved */
	[DPL_TIMESTAMP_SEL]				= BIT(7),
	[TAG_TIMESTAMP_LSB]				= GENMASK(12, 8),
	/* Bits 13-15 reserved */
	[NAT_TIMESTAMP_LSB]				= GENMASK(20, 16),
	/* Bits 21-31 reserved */
};
IPA_REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);

static const u32 ipa_reg_timers_xo_clk_div_cfg_field[] = {
	[DIV_VALUE]					= GENMASK(8, 0),
	/* Bits 9-30 reserved */
	[DIV_ENABLE]					= BIT(31),
};
IPA_REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);

static const u32 ipa_reg_timers_pulse_gran_cfg_field[] = {
	[PULSE_GRAN_0]					= GENMASK(2, 0),
	[PULSE_GRAN_1]					= GENMASK(5, 3),
	[PULSE_GRAN_2]					= GENMASK(8, 6),
	/* Bits 9-31 reserved */
};
IPA_REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);

static const u32 ipa_reg_src_rsrc_grp_01_rsrc_type_n_field[] = {
	[RSRC_GRP_X_MIN_LIM]				= GENMASK(5, 0),
	/* Bits 6-7 reserved */
	[RSRC_GRP_X_MAX_LIM]				= GENMASK(13, 8),
	/* Bits 14-15 reserved */
	[RSRC_GRP_Y_MIN_LIM]				= GENMASK(21, 16),
	/* Bits 22-23 reserved */
	[RSRC_GRP_Y_MAX_LIM]				= GENMASK(29, 24),
	/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE_N, src_rsrc_grp_01_rsrc_type_n,
		      0x00000400, 0x0020);

static const u32 ipa_reg_src_rsrc_grp_23_rsrc_type_n_field[] = {
	[RSRC_GRP_X_MIN_LIM]				= GENMASK(5, 0),
	/* Bits 6-7 reserved */
	[RSRC_GRP_X_MAX_LIM]				= GENMASK(13, 8),
	/* Bits 14-15 reserved */
	[RSRC_GRP_Y_MIN_LIM]				= GENMASK(21, 16),
	/* Bits 22-23 reserved */
	[RSRC_GRP_Y_MAX_LIM]				= GENMASK(29, 24),
	/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE_N, src_rsrc_grp_23_rsrc_type_n,
		      0x00000404, 0x0020);

static const u32 ipa_reg_src_rsrc_grp_45_rsrc_type_n_field[] = {
	[RSRC_GRP_X_MIN_LIM]				= GENMASK(5, 0),
	/* Bits 6-7 reserved */
	[RSRC_GRP_X_MAX_LIM]				= GENMASK(13, 8),
	/* Bits 14-15 reserved */
	[RSRC_GRP_Y_MIN_LIM]				= GENMASK(21, 16),
	/* Bits 22-23 reserved */
	[RSRC_GRP_Y_MAX_LIM]				= GENMASK(29, 24),
	/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE_N, src_rsrc_grp_45_rsrc_type_n,
		      0x00000408, 0x0020);

static const u32 ipa_reg_src_rsrc_grp_67_rsrc_type_n_field[] = {
	[RSRC_GRP_X_MIN_LIM]				= GENMASK(5, 0),
	/* Bits 6-7 reserved */
	[RSRC_GRP_X_MAX_LIM]				= GENMASK(13, 8),
	/* Bits 14-15 reserved */
	[RSRC_GRP_Y_MIN_LIM]				= GENMASK(21, 16),
	/* Bits 22-23 reserved */
	[RSRC_GRP_Y_MAX_LIM]				= GENMASK(29, 24),
	/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE_N, src_rsrc_grp_67_rsrc_type_n,
		      0x0000040c, 0x0020);

static const u32 ipa_reg_dst_rsrc_grp_01_rsrc_type_n_field[] = {
	[RSRC_GRP_X_MIN_LIM]				= GENMASK(5, 0),
	/* Bits 6-7 reserved */
	[RSRC_GRP_X_MAX_LIM]				= GENMASK(13, 8),
	/* Bits 14-15 reserved */
	[RSRC_GRP_Y_MIN_LIM]				= GENMASK(21, 16),
	/* Bits 22-23 reserved */
	[RSRC_GRP_Y_MAX_LIM]				= GENMASK(29, 24),
	/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE_N, dst_rsrc_grp_01_rsrc_type_n,
		      0x00000500, 0x0020);

static const u32 ipa_reg_dst_rsrc_grp_23_rsrc_type_n_field[] = {
	[RSRC_GRP_X_MIN_LIM]				= GENMASK(5, 0),
	/* Bits 6-7 reserved */
	[RSRC_GRP_X_MAX_LIM]				= GENMASK(13, 8),
	/* Bits 14-15 reserved */
	[RSRC_GRP_Y_MIN_LIM]				= GENMASK(21, 16),
	/* Bits 22-23 reserved */
	[RSRC_GRP_Y_MAX_LIM]				= GENMASK(29, 24),
	/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE_N, dst_rsrc_grp_23_rsrc_type_n,
		      0x00000504, 0x0020);

static const u32 ipa_reg_dst_rsrc_grp_45_rsrc_type_n_field[] = {
	[RSRC_GRP_X_MIN_LIM]				= GENMASK(5, 0),
	/* Bits 6-7 reserved */
	[RSRC_GRP_X_MAX_LIM]				= GENMASK(13, 8),
	/* Bits 14-15 reserved */
	[RSRC_GRP_Y_MIN_LIM]				= GENMASK(21, 16),
	/* Bits 22-23 reserved */
	[RSRC_GRP_Y_MAX_LIM]				= GENMASK(29, 24),
	/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE_N, dst_rsrc_grp_45_rsrc_type_n,
		      0x00000508, 0x0020);

static const u32 ipa_reg_dst_rsrc_grp_67_rsrc_type_n_field[] = {
	[RSRC_GRP_X_MIN_LIM]				= GENMASK(5, 0),
	/* Bits 6-7 reserved */
	[RSRC_GRP_X_MAX_LIM]				= GENMASK(13, 8),
	/* Bits 14-15 reserved */
	[RSRC_GRP_Y_MIN_LIM]				= GENMASK(21, 16),
	/* Bits 22-23 reserved */
	[RSRC_GRP_Y_MAX_LIM]				= GENMASK(29, 24),
	/* Bits 30-31 reserved */
};
IPA_REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE_N, dst_rsrc_grp_67_rsrc_type_n,
		      0x0000050c, 0x0020);

static const u32 ipa_reg_endp_init_cfg_n_field[] = {
	[FRAG_OFFLOAD_EN]				= BIT(0),
	[CS_OFFLOAD_EN]					= GENMASK(2, 1),
	[CS_METADATA_HDR_OFFSET]			= GENMASK(6, 3),
	/* Bit 7 reserved */
	[CS_GEN_QMB_MASTER_SEL]				= BIT(8),
	/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_CFG_N, endp_init_cfg_n, 0x00000808, 0x0070);

static const u32 ipa_reg_endp_init_nat_n_field[] = {
	[ENDP_NAT_EN]					= GENMASK(1, 0),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_NAT_N, endp_init_nat_n, 0x0000080c, 0x0070);

static const u32 ipa_reg_endp_init_hdr_n_field[] = {
	[HDR_LEN]					= GENMASK(5, 0),
	[HDR_OFST_METADATA_VALID]			= BIT(6),
	[HDR_OFST_METADATA]				= GENMASK(12, 7),
	[HDR_ADDITIONAL_CONST_LEN]			= GENMASK(18, 13),
	[HDR_OFST_PKT_SIZE_VALID]			= BIT(19),
	[HDR_OFST_PKT_SIZE]				= GENMASK(25, 20),
	[HDR_A5_MUX]					= BIT(26),
	[HDR_LEN_INC_DEAGG_HDR]				= BIT(27),
	[HDR_LEN_MSB]					= GENMASK(29, 28),
	[HDR_OFST_METADATA_MSB]				= GENMASK(31, 30),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_N, endp_init_hdr_n, 0x00000810, 0x0070);

static const u32 ipa_reg_endp_init_hdr_ext_n_field[] = {
	[HDR_ENDIANNESS]				= BIT(0),
	[HDR_TOTAL_LEN_OR_PAD_VALID]			= BIT(1),
	[HDR_TOTAL_LEN_OR_PAD]				= BIT(2),
	[HDR_PAYLOAD_LEN_INC_PADDING]			= BIT(3),
	[HDR_TOTAL_LEN_OR_PAD_OFFSET]			= GENMASK(9, 4),
	[HDR_PAD_TO_ALIGNMENT]				= GENMASK(13, 10),
	/* Bits 14-15 reserved */
	[HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB]		= GENMASK(17, 16),
	[HDR_OFST_PKT_SIZE_MSB]				= GENMASK(19, 18),
	[HDR_ADDITIONAL_CONST_LEN_MSB]			= GENMASK(21, 20),
	/* Bits 22-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT_N, endp_init_hdr_ext_n,
		      0x00000814, 0x0070);

IPA_REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK_N, endp_init_hdr_metadata_mask_n,
	       0x00000818, 0x0070);

static const u32 ipa_reg_endp_init_mode_n_field[] = {
	[ENDP_MODE]					= GENMASK(2, 0),
	/* Bit 3 reserved */
	[DEST_PIPE_INDEX]				= GENMASK(8, 4),
	/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_MODE_N, endp_init_mode_n, 0x00000820, 0x0070);

static const u32 ipa_reg_endp_init_aggr_n_field[] = {
	[ENDP_AGGR_EN]					= GENMASK(1, 0),
	[ENDP_AGGR_TYPE]				= GENMASK(4, 2),
	[ENDP_AGGR_BYTE_LIMIT]				= GENMASK(10, 5),
	/* Bit 11 reserved */
	[ENDP_AGGR_TIME_LIMIT]				= GENMASK(16, 12),
	[ENDP_AGGR_PKT_LIMIT]				= GENMASK(22, 17),
	[ENDP_AGGR_SW_EOF_ACTIVE]			= BIT(23),
	[ENDP_AGGR_FORCE_CLOSE]				= BIT(24),
	/* Bit 25 reserved */
	[ENDP_AGGR_HARD_BYTE_LIMIT_ENABLE]	 	= BIT(26),
	[ENDP_AGGR_GRAN_SEL]				= BIT(27),
	/* Bits 28-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_AGGR_N, endp_init_aggr_n, 0x00000824, 0x0070);

static const u32 ipa_reg_endp_init_hol_block_en_n_field[] = {
	[HOL_BLOCK_EN]				= BIT(0),
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN_N, endp_init_hol_block_en_n,
		      0x0000082c, 0x0070);

static const u32 ipa_reg_endp_init_hol_block_timer_n_field[] = {
	[HOLB_TIMER_TIME_LIMIT]				= GENMASK(4, 0),
	/* Bits 5-7 reserved */
	[HOLB_TIMER_GRAN_SEL]				= BIT(8),
	/* Bits 9-31 reserved */
};
IPA_REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER_N, endp_init_hol_block_timer_n,
			0x00000830, 0x0070);

static const struct ipa_reg *ipa_reg[] = {
	[IPA_REG_COMP_CFG]		= &ipa_reg_comp_cfg,
	[IPA_REG_CLKON_CFG]		= &ipa_reg_clkon_cfg,
	[IPA_REG_ROUTE]			= &ipa_reg_route,
	[IPA_REG_SHARED_MEM_SIZE]	= &ipa_reg_shared_mem_size,
	[IPA_REG_QSB_MAX_WRITES]	= &ipa_reg_qsb_max_writes,
	[IPA_REG_QSB_MAX_READS]		= &ipa_reg_qsb_max_reads,
	[IPA_REG_FILT_ROUT_HASH_EN]	= &ipa_reg_filt_rout_hash_en,
	[IPA_REG_FILT_ROUT_HASH_FLUSH]	= &ipa_reg_filt_rout_hash_flush,
	[IPA_REG_STATE_AGGR_ACTIVE]	= &ipa_reg_state_aggr_active,
	[IPA_REG_LOCAL_PKT_PROC_CNTXT]	= &ipa_reg_local_pkt_proc_cntxt,
	[IPA_REG_AGGR_FORCE_CLOSE]	= &ipa_reg_aggr_force_close,
	[IPA_REG_TX_CFG]		= &ipa_reg_tx_cfg,
	[IPA_REG_FLAVOR_0]		= &ipa_reg_flavor_0,
	[IPA_REG_IDLE_INDICATION_CFG]	= &ipa_reg_idle_indication_cfg,
	[IPA_REG_QTIME_TIMESTAMP_CFG]	= &ipa_reg_qtime_timestamp_cfg,
	[IPA_REG_TIMERS_XO_CLK_DIV_CFG]	= &ipa_reg_timers_xo_clk_div_cfg,
	[IPA_REG_TIMERS_PULSE_GRAN_CFG]	= &ipa_reg_timers_pulse_gran_cfg,
	[IPA_REG_SRC_RSRC_GRP_01_RSRC_TYPE_N] =
					&ipa_reg_src_rsrc_grp_01_rsrc_type_n,
	[IPA_REG_SRC_RSRC_GRP_23_RSRC_TYPE_N] =
					&ipa_reg_src_rsrc_grp_23_rsrc_type_n,
	[IPA_REG_SRC_RSRC_GRP_45_RSRC_TYPE_N] =
					&ipa_reg_src_rsrc_grp_45_rsrc_type_n,
	[IPA_REG_SRC_RSRC_GRP_67_RSRC_TYPE_N] =
					&ipa_reg_src_rsrc_grp_67_rsrc_type_n,
	[IPA_REG_DST_RSRC_GRP_01_RSRC_TYPE_N] =
					&ipa_reg_dst_rsrc_grp_01_rsrc_type_n,
	[IPA_REG_DST_RSRC_GRP_23_RSRC_TYPE_N] =
					&ipa_reg_dst_rsrc_grp_23_rsrc_type_n,
	[IPA_REG_DST_RSRC_GRP_45_RSRC_TYPE_N] =
					&ipa_reg_dst_rsrc_grp_45_rsrc_type_n,
	[IPA_REG_DST_RSRC_GRP_67_RSRC_TYPE_N] =
					&ipa_reg_dst_rsrc_grp_67_rsrc_type_n,
	[IPA_REG_ENDP_INIT_CFG_N]	= &ipa_reg_endp_init_cfg_n,
	[IPA_REG_ENDP_INIT_NAT_N]	= &ipa_reg_endp_init_nat_n,
	[IPA_REG_ENDP_INIT_HDR_N]	= &ipa_reg_endp_init_hdr_n,
	[IPA_REG_ENDP_INIT_HDR_EXT_N]	= &ipa_reg_endp_init_hdr_ext_n,
	[IPA_REG_ENDP_INIT_HDR_METADATA_MASK_N]	=
					&ipa_reg_endp_init_hdr_metadata_mask_n,
	[IPA_REG_ENDP_INIT_MODE_N]	= &ipa_reg_endp_init_mode_n,
	[IPA_REG_ENDP_INIT_AGGR_N]	= &ipa_reg_endp_init_aggr_n,
	[IPA_REG_ENDP_INIT_HOL_BLOCK_EN_N] =
					&ipa_reg_endp_init_hol_block_en_n,
	[IPA_REG_ENDP_INIT_HOL_BLOCK_TIMER_N] =
					&ipa_reg_endp_init_hol_block_timer_n,
};

const struct ipa_regs ipa_regs_v4_5 = {
	.reg_count	= ARRAY_SIZE(ipa_reg),
	.reg		= ipa_reg,
};