From 732d6215afc86b51c42fa7b4a587985a36cbc0c8 Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Tue, 4 Mar 2014 11:03:13 +0000 Subject: usb: Add support for Synopsis H20AHB EHCI host controller. Signed-off-by: Liviu Dudau Signed-off-by: Jon Medhurst --- drivers/usb/host/Kconfig | 7 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-h20ahb.c | 341 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 349 insertions(+) create mode 100644 drivers/usb/host/ehci-h20ahb.c diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 3d9e54062d62..191f91c07416 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -158,6 +158,13 @@ config USB_EHCI_HCD_SPEAR Enables support for the on-chip EHCI controller on ST SPEAr chips. +config USB_EHCI_HCD_SYNOPSYS + tristate "Support for Synopsys Host-AHB USB 2.0 controller" + depends on USB_EHCI_HCD + ---help--- + Enable support for onchip USB controllers based on DesignWare USB 2.0 + Host-AHB Controller IP from Synopsys. + config USB_EHCI_HCD_AT91 tristate "Support for Atmel on-chip EHCI USB controller" depends on USB_EHCI_HCD && ARCH_AT91 diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 7530468c9a4f..b6de8c7d4736 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o obj-$(CONFIG_USB_EHCI_HCD_OMAP) += ehci-omap.o obj-$(CONFIG_USB_EHCI_HCD_ORION) += ehci-orion.o obj-$(CONFIG_USB_EHCI_HCD_SPEAR) += ehci-spear.o +obj-$(CONFIG_USB_EHCI_HCD_SYNOPSYS) += ehci-h20ahb.o obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o obj-$(CONFIG_USB_EHCI_MSM) += ehci-msm.o diff --git a/drivers/usb/host/ehci-h20ahb.c b/drivers/usb/host/ehci-h20ahb.c new file mode 100644 index 000000000000..3ee3c7aa6e5b --- /dev/null +++ b/drivers/usb/host/ehci-h20ahb.c @@ -0,0 +1,341 @@ +/* + * Copyright (C) 2007-2013 Texas Instruments, Inc. + * Author: Vikram Pandita + * Author: Anand Gadiyar + * Author: Keshava Munegowda + * Author: Roger Quadros + * + * Copyright (C) 2009 Nokia Corporation + * Contact: Felipe Balbi + * + * Based on ehci-omap.c - driver for USBHOST on OMAP3/4 processors + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ehci.h" + +#define H20AHB_HS_USB_PORTS 1 + +/* EHCI Synopsys-specific Register Set */ +#define EHCI_INSNREG04 (0xA0) +#define EHCI_INSNREG04_DISABLE_UNSUSPEND (1 << 5) +#define EHCI_INSNREG05_ULPI (0xA4) +#define EHCI_INSNREG05_ULPI_CONTROL_SHIFT 31 +#define EHCI_INSNREG05_ULPI_PORTSEL_SHIFT 24 +#define EHCI_INSNREG05_ULPI_OPSEL_SHIFT 22 +#define EHCI_INSNREG05_ULPI_REGADD_SHIFT 16 +#define EHCI_INSNREG05_ULPI_EXTREGADD_SHIFT 8 +#define EHCI_INSNREG05_ULPI_WRDATA_SHIFT 0 + +#define DRIVER_DESC "H20AHB-EHCI Host Controller driver" + +static const char hcd_name[] = "ehci-h20ahb"; + +/*-------------------------------------------------------------------------*/ + +struct h20ahb_hcd { + struct usb_phy *phy[H20AHB_HS_USB_PORTS]; /* one PHY for each port */ + int nports; +}; + +static inline void ehci_write(void __iomem *base, u32 reg, u32 val) +{ + __raw_writel(val, base + reg); +} + +static inline u32 ehci_read(void __iomem *base, u32 reg) +{ + return __raw_readl(base + reg); +} + +/* configure so an HC device and id are always provided */ +/* always called with process context; sleeping is OK */ + +static struct hc_driver __read_mostly ehci_h20ahb_hc_driver; + +static const struct ehci_driver_overrides ehci_h20ahb_overrides __initdata = { + .extra_priv_size = sizeof(struct h20ahb_hcd), +}; + +static int ehci_h20ahb_phy_read(struct usb_phy *x, u32 reg) +{ + u32 val = (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) | + (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) | + (3 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) | + (reg << EHCI_INSNREG05_ULPI_REGADD_SHIFT); + ehci_write(x->io_priv, 0, val); + while ((val = ehci_read(x->io_priv, 0)) & + (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT)); + return val & 0xff; +} + +static int ehci_h20ahb_phy_write(struct usb_phy *x, u32 val, u32 reg) +{ + u32 v = (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT) | + (1 << EHCI_INSNREG05_ULPI_PORTSEL_SHIFT) | + (2 << EHCI_INSNREG05_ULPI_OPSEL_SHIFT) | + (reg << EHCI_INSNREG05_ULPI_REGADD_SHIFT) | + (val & 0xff); + ehci_write(x->io_priv, 0, v); + while ((v = ehci_read(x->io_priv, 0)) & + (1 << EHCI_INSNREG05_ULPI_CONTROL_SHIFT)); + return 0; +} + +static struct usb_phy_io_ops ehci_h20ahb_phy_io_ops = { + .read = ehci_h20ahb_phy_read, + .write = ehci_h20ahb_phy_write, +}; + + +/** + * ehci_hcd_h20ahb_probe - initialize Synopsis-based HCDs + * + * Allocates basic resources for this USB host controller, and + * then invokes the start() method for the HCD associated with it + * through the hotplug entry's driver_data. + */ +static int ehci_hcd_h20ahb_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + struct usb_hcd *hcd; + void __iomem *regs; + int ret; + int irq; + int i; + struct h20ahb_hcd *h20ahb; + + if (usb_disabled()) + return -ENODEV; + + /* if (!dev->parent) { + dev_err(dev, "Missing parent device\n"); + return -ENODEV; + }*/ + + /* For DT boot, get platform data from parent. i.e. usbhshost */ + /*if (dev->of_node) { + pdata = dev_get_platdata(dev->parent); + dev->platform_data = pdata; + } + + if (!pdata) { + dev_err(dev, "Missing platform data\n"); + return -ENODEV; + }*/ + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "EHCI irq failed\n"); + return -ENODEV; + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + regs = devm_ioremap_resource(dev, res); + if (IS_ERR(regs)) + return PTR_ERR(regs); + + /* + * Right now device-tree probed devices don't get dma_mask set. + * Since shared usb code relies on it, set it here for now. + * Once we have dma capability bindings this can go away. + */ + ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); + if (ret) + return ret; + + ret = -ENODEV; + hcd = usb_create_hcd(&ehci_h20ahb_hc_driver, dev, + dev_name(dev)); + if (!hcd) { + dev_err(dev, "Failed to create HCD\n"); + return -ENOMEM; + } + + hcd->rsrc_start = res->start; + hcd->rsrc_len = resource_size(res); + hcd->regs = regs; + hcd_to_ehci(hcd)->caps = regs; + + h20ahb = (struct h20ahb_hcd *)hcd_to_ehci(hcd)->priv; + h20ahb->nports = 1; + + platform_set_drvdata(pdev, hcd); + + /* get the PHY devices if needed */ + for (i = 0 ; i < h20ahb->nports ; i++) { + struct usb_phy *phy; + + /* get the PHY device */ +#if 0 + if (dev->of_node) + phy = devm_usb_get_phy_by_phandle(dev, "phys", i); + else + phy = devm_usb_get_phy_dev(dev, i); +#endif + phy = otg_ulpi_create(&ehci_h20ahb_phy_io_ops, 0); + if (IS_ERR(phy)) { + ret = PTR_ERR(phy); + dev_err(dev, "Can't get PHY device for port %d: %d\n", + i, ret); + goto err_phy; + } + phy->dev = dev; + usb_add_phy_dev(phy); + + h20ahb->phy[i] = phy; + phy->io_priv = hcd->regs + EHCI_INSNREG05_ULPI; + +#if 0 + usb_phy_init(h20ahb->phy[i]); + /* bring PHY out of suspend */ + usb_phy_set_suspend(h20ahb->phy[i], 0); +#endif + } + + /* make the first port's phy the one used by hcd as well */ + hcd->phy = h20ahb->phy[0]; + + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + + /* + * An undocumented "feature" in the H20AHB EHCI controller, + * causes suspended ports to be taken out of suspend when + * the USBCMD.Run/Stop bit is cleared (for example when + * we do ehci_bus_suspend). + * This breaks suspend-resume if the root-hub is allowed + * to suspend. Writing 1 to this undocumented register bit + * disables this feature and restores normal behavior. + */ + ehci_write(regs, EHCI_INSNREG04, + EHCI_INSNREG04_DISABLE_UNSUSPEND); + + ret = usb_add_hcd(hcd, irq, IRQF_SHARED); + if (ret) { + dev_err(dev, "failed to add hcd with err %d\n", ret); + goto err_pm_runtime; + } + device_wakeup_enable(hcd->self.controller); + + /* + * Bring PHYs out of reset for non PHY modes. + * Even though HSIC mode is a PHY-less mode, the reset + * line exists between the chips and can be modelled + * as a PHY device for reset control. + */ + for (i = 0; i < h20ahb->nports; i++) { + usb_phy_init(h20ahb->phy[i]); + /* bring PHY out of suspend */ + usb_phy_set_suspend(h20ahb->phy[i], 0); + } + + return 0; + +err_pm_runtime: + pm_runtime_put_sync(dev); + +err_phy: + for (i = 0; i < h20ahb->nports; i++) { + if (h20ahb->phy[i]) + usb_phy_shutdown(h20ahb->phy[i]); + } + + usb_put_hcd(hcd); + + return ret; +} + + +/** + * ehci_hcd_h20ahb_remove - shutdown processing for EHCI HCDs + * @pdev: USB Host Controller being removed + * + * Reverses the effect of usb_ehci_hcd_h20ahb_probe(), first invoking + * the HCD's stop() method. It is always called from a thread + * context, normally "rmmod", "apmd", or something similar. + */ +static int ehci_hcd_h20ahb_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct usb_hcd *hcd = dev_get_drvdata(dev); + struct h20ahb_hcd *h20ahb = (struct h20ahb_hcd *)hcd_to_ehci(hcd)->priv; + int i; + + usb_remove_hcd(hcd); + + for (i = 0; i < h20ahb->nports; i++) { + if (h20ahb->phy[i]) + usb_phy_shutdown(h20ahb->phy[i]); + } + + usb_put_hcd(hcd); + pm_runtime_put_sync(dev); + pm_runtime_disable(dev); + + return 0; +} + +static const struct of_device_id h20ahb_ehci_dt_ids[] = { + { .compatible = "snps,ehci-h20ahb" }, + { } +}; + +MODULE_DEVICE_TABLE(of, h20ahb_ehci_dt_ids); + +static struct platform_driver ehci_hcd_h20ahb_driver = { + .probe = ehci_hcd_h20ahb_probe, + .remove = ehci_hcd_h20ahb_remove, + .shutdown = usb_hcd_platform_shutdown, + /*.suspend = ehci_hcd_h20ahb_suspend, */ + /*.resume = ehci_hcd_h20ahb_resume, */ + .driver = { + .name = hcd_name, + .of_match_table = h20ahb_ehci_dt_ids, + } +}; + +/*-------------------------------------------------------------------------*/ + +static int __init ehci_h20ahb_init(void) +{ + if (usb_disabled()) + return -ENODEV; + + pr_info("%s: " DRIVER_DESC "\n", hcd_name); + + ehci_init_driver(&ehci_h20ahb_hc_driver, &ehci_h20ahb_overrides); + return platform_driver_register(&ehci_hcd_h20ahb_driver); +} +module_init(ehci_h20ahb_init); + +static void __exit ehci_h20ahb_cleanup(void) +{ + platform_driver_unregister(&ehci_hcd_h20ahb_driver); +} +module_exit(ehci_h20ahb_cleanup); + +MODULE_ALIAS("platform:ehci-h20ahb"); +MODULE_AUTHOR("Liviu Dudau "); + +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 8d918853ca7a831cf0792c0a1d327520e25414ca Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Tue, 4 Mar 2014 11:21:41 +0000 Subject: phy: Enable USB PHY support for arm64. Signed-off-by: Liviu Dudau Signed-off-by: Jon Medhurst --- drivers/usb/phy/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig index 416e0c8cf6ff..0fd825278bdd 100644 --- a/drivers/usb/phy/Kconfig +++ b/drivers/usb/phy/Kconfig @@ -232,7 +232,7 @@ config USB_RCAR_GEN2_PHY config USB_ULPI bool "Generic ULPI Transceiver Driver" - depends on ARM + depends on ARM || ARM64 help Enable this to support ULPI connected USB OTG transceivers which are likely found on embedded boards. -- cgit v1.2.3 From 7270373c91063d788c7c5c321b7d0f489900489b Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Tue, 4 Mar 2014 11:22:32 +0000 Subject: phy: Add SMSC USB334x PHY IDs. Signed-off-by: Liviu Dudau Signed-off-by: Jon Medhurst --- drivers/usb/phy/phy-ulpi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/usb/phy/phy-ulpi.c b/drivers/usb/phy/phy-ulpi.c index 17ea3f271bd8..4e3877c329f2 100644 --- a/drivers/usb/phy/phy-ulpi.c +++ b/drivers/usb/phy/phy-ulpi.c @@ -48,6 +48,7 @@ static struct ulpi_info ulpi_ids[] = { ULPI_INFO(ULPI_ID(0x04cc, 0x1504), "NXP ISP1504"), ULPI_INFO(ULPI_ID(0x0424, 0x0006), "SMSC USB331x"), ULPI_INFO(ULPI_ID(0x0424, 0x0007), "SMSC USB3320"), + ULPI_INFO(ULPI_ID(0x0424, 0x0009), "SMSC USB334x"), ULPI_INFO(ULPI_ID(0x0451, 0x1507), "TI TUSB1210"), }; -- cgit v1.2.3 From 88c3ee08afa8b662b4d1f36b435d5e4717fcc98a Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Mon, 10 Mar 2014 10:49:22 +0000 Subject: usb: Use usb_hub_set_port_power() in hub_power_on() rather than equivalent code. hub_power_on() uses code to set port power that is equivalent to usb_hub_set_port_power(). Use that function directly and reduce code size. Signed-off-by: Liviu Dudau Signed-off-by: Jon Medhurst --- drivers/usb/core/hub.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c index 229a73f64304..fea0a39d5d3b 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -833,11 +833,8 @@ static unsigned hub_power_on(struct usb_hub *hub, bool do_delay) dev_dbg(hub->intfdev, "trying to enable port power on " "non-switchable hub\n"); for (port1 = 1; port1 <= hub->hdev->maxchild; port1++) - if (hub->ports[port1 - 1]->power_is_on) - set_port_feature(hub->hdev, port1, USB_PORT_FEAT_POWER); - else - usb_clear_port_feature(hub->hdev, port1, - USB_PORT_FEAT_POWER); + usb_hub_set_port_power(hub->hdev, hub, port1, + hub->ports[port1 - 1]->power_is_on); /* Wait at least 100 msec for power to become stable */ delay = max(pgood_delay, (unsigned) 100); -- cgit v1.2.3 From 1fbe2a25bbfe57ce33d565a5ae39e8266d15eefa Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Mon, 10 Mar 2014 10:55:37 +0000 Subject: usb: Enable support for 64bit EHCI host controllers in arm64. arm64 architecture handles correctly 64bit DMAs and can enable support for 64bit EHCI host controllers. Signed-off-by: Liviu Dudau Signed-off-by: Jon Medhurst --- drivers/usb/host/ehci-hcd.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 81cda09b47e3..d1a48e49c0e8 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -590,11 +590,16 @@ static int ehci_run (struct usb_hcd *hcd) */ hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); if (HCC_64BIT_ADDR(hcc_params)) { - ehci_writel(ehci, 0, &ehci->regs->segment); -#if 0 -// this is deeply broken on almost all architectures +#if CONFIG_ARM64 + ehci_writel(ehci, ehci->periodic_dma >> 32, &ehci->regs->segment); + /* + * this is deeply broken on almost all architectures + * but arm64 can use it so enable it + */ if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) ehci_info(ehci, "enabled 64bit DMA\n"); +#else + ehci_writel(ehci, 0, &ehci->regs->segment); #endif } -- cgit v1.2.3 From 7c38d69e7238224e8efceef09ee51f0d726c710d Mon Sep 17 00:00:00 2001 From: Mark Brown Date: Thu, 8 May 2014 12:09:03 +0100 Subject: dtc: Use general include directory Since newer DT bindings include references to include/dt-bindings we need to make this available to build DTs using them. Upstream has a number of reworkings which are much more invasive but featureful, just include a minimal fix. Signed-off-by: Mark Brown Signed-off-by: Jon Medhurst --- scripts/Makefile.lib | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 6a5b0decb797..6928bb298497 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -153,6 +153,7 @@ dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \ -I$(srctree)/arch/$(SRCARCH)/boot/dts \ -I$(srctree)/arch/$(SRCARCH)/boot/dts/include \ -I$(srctree)/drivers/of/testcase-data \ + -I$(srctree)/include \ -undef -D__DTS__ # Finds the multi-part object the current object will be linked into -- cgit v1.2.3 From 287a4cddab094399de0031ee77fdf0e749f912b1 Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Fri, 4 Apr 2014 15:50:54 +0100 Subject: Add kernel config fragment for Juno Signed-off-by: Jon Medhurst Signed-off-by: Jon Medhurst --- linaro/configs/juno.conf | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 linaro/configs/juno.conf diff --git a/linaro/configs/juno.conf b/linaro/configs/juno.conf new file mode 100644 index 000000000000..5f55e61fcfa1 --- /dev/null +++ b/linaro/configs/juno.conf @@ -0,0 +1,20 @@ +CONFIG_COMPAT=y +CONFIG_SMSC911X=y +CONFIG_INPUT_EVDEV=y +CONFIG_SERIO_AMBAKMI=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_I2C=y +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_USB_HIDDEV=y +CONFIG_SCSI=y +CONFIG_BLK_DEV_SD=y +CONFIG_USB_STORAGE=y +CONFIG_USB=y +CONFIG_USB_ULPI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_SYNOPSYS=y +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_OHCI_HCD=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PL031=y -- cgit v1.2.3 From dd64ab2e3b26a6a43856dc4879262b9a37a66637 Mon Sep 17 00:00:00 2001 From: Liviu Dudau Date: Thu, 6 Jun 2013 10:41:39 +0100 Subject: arm64: Add Juno platform support This is a squashed down and edited version of the dts in ARM's juno tree at https://github.com/ARM-software/linux. Signed-off-by: Liviu Dudau Signed-off-by: Jon Medhurst --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/juno.dts | 480 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 481 insertions(+) create mode 100644 arch/arm64/boot/dts/juno.dts diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index c52bdb051f66..f1a9623a4a6f 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb targets += dtbs diff --git a/arch/arm64/boot/dts/juno.dts b/arch/arm64/boot/dts/juno.dts new file mode 100644 index 000000000000..71a35474429b --- /dev/null +++ b/arch/arm64/boot/dts/juno.dts @@ -0,0 +1,480 @@ +/* + * ARM Ltd. Juno Plaform + * + * Fast Models FVP v2 support + */ + +/dts-v1/; + +#include + +/ { + model = "Juno"; + compatible = "arm,juno", "arm,vexpress"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &soc_uart0; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster1 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + + cluster0 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + }; + }; + + CPU0:cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "vlittle"; + }; + + CPU1:cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "vlittle"; + }; + + CPU2:cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x102>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "vlittle"; + }; + + CPU3:cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x0 0x103>; + enable-method = "psci"; + clocks = <&scpi_dvfs 1>; + clock-names = "vlittle"; + }; + + CPU4:cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "vbig"; + }; + + CPU5:cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&scpi_dvfs 0>; + clock-names = "vbig"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x0 0x80000000> /*, + <0x00000008 0x80000000 0x1 0x80000000> */; + }; + + /* memory@14000000 { + device_type = "memory"; + reg = <0x00000000 0x14000000 0x0 0x02000000>; + }; */ + + gic: interrupt-controller@2c001000 { + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x2c010000 0 0x1000>, + <0x0 0x2c02f000 0 0x1000>, + <0x0 0x2c04f000 0 0x2000>, + <0x0 0x2c06f000 0 0x2000>; + interrupts = ; + }; + + msi0: msi@2c1c0000 { + compatible = "arm,gic-msi"; + reg = <0x0 0x2c1c0000 0 0x10000 + 0x0 0x2c1d0000 0 0x10000 + 0x0 0x2c1e0000 0 0x10000 + 0x0 0x2c1f0000 0 0x10000>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + }; + + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0xC4000001>; + cpu_off = <0x84000002>; + cpu_on = <0xC4000003>; + migrate = <0xC4000005>; + }; + + pci0: pci@30000000 { + compatible = "arm,pcie-xr3"; + device_type = "pci"; + reg = <0 0x7ff30000 0 0x1000 + 0 0x7ff20000 0 0x10000 + 0 0x40000000 0 0x10000000>; + bus-range = <0 255>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x00 0x5ff00000 0x0 0x00100000 + 0x02000000 0x0 0x00000000 0x40 0x00000000 0x0 0x80000000 + 0x42000000 0x0 0x80000000 0x40 0x80000000 0x0 0x80000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 136 4 + 0 0 0 2 &gic 0 137 4 + 0 0 0 3 &gic 0 138 4 + 0 0 0 4 &gic 0 139 4>; + }; + + scpi: mhu@2b1f0000 { + compatible = "arm,mhu"; + reg = <0x0 0x2b1f0000 0x0 0x10000>, /* MHU registers */ + <0x0 0x2e000000 0x0 0x10000>; /* Payload area */ + interrupts = <0 36 4>, /* low priority interrupt */ + <0 35 4>; /* high priority interrupt */ + }; + + clocks { + compatible = "arm,scpi-clks"; + + scpi_dvfs: scpi_clocks@0 { + compatible = "arm,scpi-clk-indexed"; + #clock-cells = <1>; + clock-indices = <0>, <1>, <2>; + clock-output-names = "vbig", "vlittle", "vgpu"; + }; + + scpi_clk: scpi_clocks@3 { + compatible = "arm,scpi-clk-range"; + #clock-cells = <1>; + clock-indices = <3>, <4>; + frequency-range = <23000000 210000000>; + clock-output-names = "pxlclk0", "pxlclk1"; + }; + + }; + + cpufreq { + compatible = "arm,scpi-cpufreq"; + }; + + soc_uartclk: refclk72738khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <7273800>; + clock-output-names = "juno:uartclk"; + }; + + soc_refclk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "juno:clk24mhz"; + }; + + mb_eth25mhz: clk25mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "ethclk25mhz"; + }; + + soc_usb48mhz: clk48mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "clk48mhz"; + }; + + soc_smc50mhz: clk50mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "smc_clk"; + }; + + soc_refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + soc_faxiclk: refclk533mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <533000000>; + clock-output-names = "faxi_clk"; + }; + + soc_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + memory-controller@7ffd0000 { + compatible = "arm,pl354", "arm,primecell"; + reg = <0 0x7ffd0000 0 0x1000>; + interrupts = <0 86 4>, + <0 87 4>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + chip5-memwidth = <16>; + }; + + dma0: dma@0x7ff00000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0x7ff00000 0 0x1000>; + interrupts = <0 95 4>, + <0 88 4>, + <0 89 4>, + <0 90 4>, + <0 91 4>, + <0 108 4>, + <0 109 4>, + <0 110 4>, + <0 111 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&soc_faxiclk>; + clock-names = "apb_pclk"; + }; + + soc_uart0: uart@7ff80000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x7ff80000 0x0 0x1000>; + interrupts = <0 83 4>; + clocks = <&soc_uartclk>, <&soc_refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + dmas = <&dma0 1 + &dma0 2>; + dma-names = "rx", "tx"; + }; + + /* this UART is reserved for secure software. + soc_uart1: uart@7ff70000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x7ff70000 0x0 0x1000>; + interrupts = <0 84 4>; + clocks = <&soc_uartclk>, <&soc_refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; */ + + ulpi_phy: phy@0 { + compatible = "phy-ulpi-generic"; + reg = <0x0 0x94 0x0 0x4>; + phy-id = <0>; + }; + + ehci@7ffc0000 { + compatible = "snps,ehci-h20ahb"; + /* compatible = "arm,h20ahb-ehci"; */ + reg = <0x0 0x7ffc0000 0x0 0x10000>; + interrupts = <0 117 4>; + clocks = <&soc_usb48mhz>; + clock-names = "otg"; + phys = <&ulpi_phy>; + }; + + ohci@0x7ffb0000 { + compatible = "generic-ohci"; + reg = <0x0 0x7ffb0000 0x0 0x10000>; + interrupts = <0 116 4>; + clocks = <&soc_usb48mhz>; + clock-names = "otg"; + }; + + i2c@0x7ffa0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0x0 0x7ffa0000 0x0 0x1000>; + interrupts = <0 104 4>; + clock-frequency = <400000>; + i2c-sda-hold-time-ns = <500>; + clocks = <&soc_smc50mhz>; + + dvi0: dvi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + }; + + dvi1: dvi-transmitter@71 { + compatible = "nxp,tda998x"; + reg = <0x71>; + }; + }; + + smb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0 0x08000000 0x04000000>, + <1 0 0 0x14000000 0x04000000>, + <2 0 0 0x18000000 0x04000000>, + <3 0 0 0x1c000000 0x04000000>, + <4 0 0 0x0c000000 0x04000000>, + <5 0 0 0x10000000 0x04000000>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 15>; + interrupt-map = <0 0 0 &gic 0 68 4>, + <0 0 1 &gic 0 69 4>, + <0 0 2 &gic 0 70 4>, + <0 0 3 &gic 0 160 4>, + <0 0 4 &gic 0 161 4>, + <0 0 5 &gic 0 162 4>, + <0 0 6 &gic 0 163 4>, + <0 0 7 &gic 0 164 4>, + <0 0 8 &gic 0 165 4>, + <0 0 9 &gic 0 166 4>, + <0 0 10 &gic 0 167 4>, + <0 0 11 &gic 0 168 4>, + <0 0 12 &gic 0 169 4>; + + motherboard { + model = "V2M-Juno"; + arm,hbi = <0x252>; + arm,vexpress,site = <0>; + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2p-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + usb@5,00000000 { + compatible = "nxp,usb-isp1763"; + reg = <5 0x00000000 0x20000>; + bus-width = <16>; + interrupts = <4>; + }; + + ethernet@2,00000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <2 0x00000000 0x10000>; + interrupts = <3>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + clocks = <&mb_eth25mhz>; + vdd33a-supply = <&soc_fixed_3v3>; /* change this */ + vddvario-supply = <&soc_fixed_3v3>; /* and this */ + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <8>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <8>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x10000>; + interrupts = <7>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x10000>; + interrupts = <9>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "timclken1", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x10000>; + interrupts = <9>; + clocks = <&soc_refclk24mhz>, <&soc_smc50mhz>; + clock-names = "timclken1", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x10000>; + interrupts = <0>; + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + }; + }; + }; + }; +}; -- cgit v1.2.3