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* tracking-qcomlt-cpuidle:
ARM: cpuidle: Add cpuidle support for QCOM cpus
devicetree: bindings: Document qcom,idle-states
devicetree: bindings: Update qcom,saw2 node bindings
ARM: qcom: Add Subsystem Power Manager (SPM) driver
firmware: qcom: scm: Support cpu power down through SCM
firmware: qcom: scm: Add qcom_scm_set_warm_boot_addr function
firmware: qcom: scm: Clean cold boot entry to export only the API
firmware: qcom: scm: Move the scm driver to drivers/firmware
ARM: qcom: Prep scm code for move to drivers/firmware
ARM: qcom: Cleanup scm interface to only export what is needed
ARM: qcom: Merge scm and scm boot code together
ARM: cpuidle: Document the code
ARM: cpuidle: Register per cpuidle device
ARM: cpuidle: Enable the ARM64 driver for both ARM32/ARM64
ARM64: cpuidle: Remove arm64 reference
ARM64: cpuidle: Rename cpu_init_idle to a common function name
ARM64: cpuidle: Replace cpu_suspend by the common ARM/ARM64 function
ARM: cpuidle: Add a cpuidle ops structure to be used for DT
ARM: cpuidle: Remove duplicate header inclusion
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* tracking-qcomlt-arm64:
arm64: defconfig: qcom: Enable restart driver
arm64: defconfig: qcom: Enable USB related drivers
arm64: defconfig: Enable extcon usb gpio driver
arm64: defconfig: add qcom specifics
arm64: qcom: Add support for Qualcomm MSM8916 SoC
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* tracking-qcomlt-dt: (48 commits)
arm64: dts: qcom: Add MSM8916 restart device node
arm64: dts: qcom: Add sdhci support for APQ8016 SBC board
arm64: dts: qcom: Add USB related device nodes on APQ8016 SBC board
arm64: dts: qcom: Switch to upstream SPMI PMIC bindings
arm64: dts: msm8916: Add thermal zones, tsens and eeprom nodes
arm: dts: msm8974: Add thermal zones, tsens and eeprom nodes
arm64: dts: qcom: msm8916: Reorder rpm/regulators
arm64: dts: qcom: msm8916: Fix whitespace
arm64: dts: qcom: Add APQ8016 SBC support
arm64: dts: qcom : msm8916: add sdhci support
arm64: dts: qcom: msm8916: Add RPM controlled regulators
arm64: dts: qcom: msm8916: Add spmi controlled regulators
arm64: dts: qcom: msm8916 Add smem nodes.
arm64: dts: qcom: msm8916 Add hwspinlock nodes.
arm64: dts: qcom: msm8916: Add reserved memory nodes.
dts:msm8916: Fix spi4_sleep duplicate error
DT: arm64: msm8916-mtp: enable spi3
DT: arm64: msm8916: add all SPI DT nodes
arm64: dts: Add Qualcomm MSM8916 & MTP8916 ids
devicetree: bindings: Document qcom,msm-id and qcom,board-id
...
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* tracking-qcomlt-iommu:
iommu: qcom: fix compiler warnings.
WIP: qcom-iommu-v0 (v3)
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* tracking-qcomlt-pmic-gpio:
pinctrl: Add support for PM8916 GPIO's and MPP's
pinctrl: qcom: fix compiler errors.
pinctrl:qcom:ssbi: Enable gpio mode
pinctrl: qcom: ssbi-pmic: promote driver to sub system level
pinctrl: Introduce pinctrl driver for Qualcomm SSBI PMIC's
mfd: pm8921: Expose pm8xxx_read_irq_status
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* tracking-qcomlt-pcie:
pci: qcom: add Kconfig to not build on arm64
pci: qcom: remove static domain name allocation
pci: qcom: Add ext_3p3v regulator support
pci: qcom: move device init to subsys_initcall_sync
pci: qcom: add msi support
pci: qcom: Add support to external phy reference clk.
pci: qcom: remove static declaration of functions.
pci: qcom: Add regulator support
pci: qcom: move dt parsing code out of probe
pci: qcom: fix unused variable warning.
pci: qcom: fix a typo in reset gpio
PCI: qcom: Add support for pcie controllers on IPQ8064
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Add the restart node so we can reboot the device.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
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Currently it have the same functionality as MTP board.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
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Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
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Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
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Add thermal zones, tsens and eeprom nodes
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
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Add compatible string definitions and supported pin functions.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
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Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
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It is used for USB ID detection on APQ8016 SBC board
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
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Qualcomm PMIC Arbiter version-2 changes from version-1 are:
- Some different register offsets.
- New channel register space, one per PMIC peripheral (ppid).
All tx traffic uses these channels.
- New observer register space. All rx trafic uses this space.
- Different command format for spmi command registers.
Reviewed-by: Sagar Dharia <sdharia@codeaurora.org>
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
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According to spmi spec a slave powers up into startup state and then
transitions into active state. Thus, the wakeup command is not required
before calling the slave's probe. The wakeup command is only needed for
slaves that are in sleep state after receiving the sleep command.
Cc: galak@codeaurora.org
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Sagar Dharia <sdharia@codeaurora.org>
Acked-by: Josh Cartwright <joshc@eso.teric.us>
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>
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Qualcomm PMIC arbiter driver already depends on ARCH_QCOM,
which could be either ARM or ARM64. New version of the PMIC
arbiter controller is available on 64 bit platforms.
Remove ARM dependency to allow driver to be build for 64 bit
platforms.
Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
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Define ARM_QCOM_CPUIDLE config item to enable cpuidle support.
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Document cpuidle states of QCOM cpus. In addition to arm-idle-state
compatible string, the ARM idle state definition must define one of the
following compatible strings -
"qcom,idle-state-ret",
"qcom,idle-state-spc",
"qcom,idle-state-pc",
The compatibles helps the SPM platform driver to use the correct idle
function when the index to the idle state is passed to the platform
driver.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Update qcom,saw2 node bindings with compatible strings to identify nodes
that provides cpuidle functionality for a particular SoC. Remove
unused compatible strings.
Update examples for different SAW nodes.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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SPM is a hardware block that controls the peripheral logic surrounding
the application cores (cpu/l$). When the core executes WFI instruction,
the SPM takes over the putting the core in low power state as
configured. The wake up for the SPM is an interrupt at the GIC, which
then completes the rest of low power mode sequence and brings the core
out of low power mode.
The SPM has a set of control registers that configure the SPMs
individually based on the type of the core and the runtime conditions.
SPM is a finite state machine block to which a sequence is provided and
it interprets the bytes and executes them in sequence. Each low power
mode that the core can enter into is provided to the SPM as a sequence.
Configure the SPM to set the core (cpu or L2) into its low power mode,
the index of the first command in the sequence is set in the SPM_CTL
register. When the core executes ARM wfi instruction, it triggers the
SPM state machine to start executing from that index. The SPM state
machine waits until the interrupt occurs and starts executing the rest
of the sequence until it hits the end of the sequence. The end of the
sequence jumps the core out of its low power mode.
Add support for an idle driver to set up the SPM to place the core in
Standby or Standalone power collapse mode when the core is idle.
Based on work by: Mahesh Sivasubramanian <msivasub@codeaurora.org>,
Ai Li <ali@codeaurora.org>, Praveen Chidambaram <pchidamb@codeaurora.org>
Original tree available at -
git://codeaurora.org/quic/la/kernel/msm-3.10.git
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Kevin Hilman <khilman@linaro.org>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Support powering down the calling cpu, by trapping into SCM. This
termination function triggers the ARM cpu to execute WFI instruction,
causing the power controller to safely power the cpu down.
Caches may be flushed before powering down the cpu. If cache controller
is set to turn off when the cpu is powered down, then the flags argument
indicates to the secure mode to flush its cache lines before executing
WFI.The warm boot reset address for the cpu should be set before the
calling into this function for the cpu to resume.
The original code for the qcom_scm_call_atomic1() comes from a patch by
Stephen Boyd [1]. The function scm_call_atomic1() has been cherry picked
and renamed to match the convention used in this file. Since there are
no users of scm_call_atomic2(), the function is not included.
[1]. https://lkml.org/lkml/2014/8/4/765
Signed-off-by: Stephen Boyd <sboyd@codeauraro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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A core can be powered down for cpuidle or when it is hotplugged off. In
either case, the warmboot return address would be different. Allow
setting the warmboot address for a specific cpu, optimize and write to
the firmware, if the address is different than the previously set
address.
Export qcom_scm_set_warm_boot_addr function move the warm boot flags to
implementation.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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We dont need to export the SCM specific cold boot flags to the platform
code. Export only a function to set the cold boot address.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Architectural changes in the ARM Linux kernel tree mandate the eventual
removal of the mach-* directories. Move the scm driver to
drivers/firmware and the scm header to include/linux to support that
removal.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Add qcom prefix to functions, etc to create a unique name space for the
scm code as it gets ready to move out of qcom specific mach dir.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Now that scom boot interface is merged we don't need export scm_call
anymore. Some other minor cleanups related to boot interface to only
export what is needed by scm_set_boot_addr().
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Put all scm related code into a single file as a first step in cleaning
up the scm interface to just expose functional behavior insteam of making
direct scm calls.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Add thermal zones, tsens and eeprom nodes
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
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This patch reorders the regulators so that the clock driver won't have issues if
it consumes a rpm regulator. If this is not done, the clock driver will probe
defer and fail to bring up the console.
Signed-off-by: Andy Gross <agross@codeaurora.org>
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This fixes the whitespace in the file to be sane.
Signed-off-by: Andy Gross <agross@codeaurora.org>
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This patch set adds support for the APQ8016 SBC.
Signed-off-by: Andy Gross <agross@codeaurora.org>
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This patch adds sdhci support.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds RPM controlled regulators.
Content of this is copied from msm 3.10 kernel tree.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds spmi controlled regulators.
Content of this is copied from msm 3.10 kernel tree.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds smem nodes which are required for smd, regulators and
others. Content of this is copied from msm 3.10 kernel tree.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds hwspinlock nodes which are required for smem and
others. Content of this is copied from msm 3.10 kernel tree.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds reserved memory nodes which are required for smem and
others. Content of this is copied from msm 3.10 kernel tree.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This enable spi3 on msm8916 mtp board
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
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Add SPI DT nodes for the SoC. Every SPI DT node has reference to
blsp dma node with relevant dma channels and appropriate pinctrl
nodes to configure SPI pins.
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
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Add qcom,msm-id and qcom,board-id to allow bootloader to identify which
device tree to boot on the MTP8916 boards.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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The top level qcom,msm-id and qcom,board-id are utilized by bootloaders
on Qualcomm MSM platforms to determine which device tree should be
utilized and passed to the kernel.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Add initial device tree support for Qualcomm MSM8916 SoC and MTP8916
evaluation board. At the current time we only boot up a single processor.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Add pwrseq support to sdcc4 which would enable a proper reset of WLAN
without ugly hacks in the board support file.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds pwrseq for both BT and WLAN which resets the WLAN and BT
just before the SDIO bus is up.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Add support for Qualcomm MSM8916 SoC in arm64 Kconfig and defconfig.
Enable MSM8916 clock, pin control, and MSM serial driver utilized by
MSM8916 and Qualcomm SoCs in general.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>
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This patch fixes below compiler error.
drivers/iommu/qcom_iommu_v0.c:941:2: error: unknown field ‘domain_has_cap’ specified in initialiser
drivers/iommu/qcom_iommu_v0.c:941:2: warning: initialisation from incompatible pointer type [enabled by default]
drivers/iommu/qcom_iommu_v0.c:941:2: warning: (near initialisation for ‘qcom_iommu_ops.add_device’) [enabled by default]
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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