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| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2024-06-12 09:54:33 +0100 |
|---|---|---|
| committer | Daniel Lezcano <daniel.lezcano@linaro.org> | 2024-07-08 18:40:11 +0200 |
| commit | ae387df1093c5f778b71f1e78870d44aa4246b8f (patch) | |
| tree | 81d608da565d5fa34f9b60b887d34bc94942efbf /arch/parisc/kernel/pdt.c | |
| parent | 400aceef16dfaa82f2c3266a20fa36071f83b7d1 (diff) | |
clocksource/drivers/mips-gic-timer: Refine rating computation
It is a good clocksource which usually go as fast as CPU core
and have a low access latency, so raise the base of rating
from Good to desired when we know that it has a stable frequency.
Increase frequency addend dividend to 10000000 (10MHz) to
reasonably accommodate multi GHz level clock, also cap rating
within current level.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Link: https://lore.kernel.org/r/20240612-mips-clks-v2-6-a57e6f49f3db@flygoat.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'arch/parisc/kernel/pdt.c')
0 files changed, 0 insertions, 0 deletions