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authorArnd Bergmann <arnd@arndb.de>2012-02-27 17:44:06 +0000
committerArnd Bergmann <arnd@arndb.de>2012-02-27 17:44:23 +0000
commitf2273ecd9a7405b867522ce03d31a9fee80c2495 (patch)
tree1c11347958061ff1e88355b8b6c0efaecad36984 /arch/arm/common
parent003e6348630aa16982c956beaf7cd0b53a3b609a (diff)
parentff424aa4c89d19082e8ae5a3351006bc8a4cd91b (diff)
Merge branch 'lpc32xx/fixes' of git://git.antcom.de/linux-2.6 into fixesfixes-3.3-rc6
* 'lpc32xx/fixes' of git://git.antcom.de/linux-2.6: (5 commits) ARM: LPC32xx: serial.c: Fixed loop limit ARM: LPC32xx: serial.c: HW bug workaround ARM: LPC32xx: irq.c: Clear latched event ARM: LPC32xx: Fix interrupt controller init ARM: LPC32xx: Fix irq on GPI_28 Update to Linux 3.3-rc5 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/common')
-rw-r--r--arch/arm/common/it8152.c7
-rw-r--r--arch/arm/common/pl330.c3
2 files changed, 2 insertions, 8 deletions
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index d1bcd7b13ebc..fb1f1cfce60c 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -320,13 +320,6 @@ err0:
return -EBUSY;
}
-/*
- * If we set up a device for bus mastering, we need to check the latency
- * timer as we don't have even crappy BIOSes to set it properly.
- * The implementation is from arch/i386/pci/i386.c
- */
-unsigned int pcibios_max_latency = 255;
-
/* ITE bridge requires setting latency timer to avoid early bus access
termination by PCI bus master devices
*/
diff --git a/arch/arm/common/pl330.c b/arch/arm/common/pl330.c
index d8e44a43047c..ff3ad2244824 100644
--- a/arch/arm/common/pl330.c
+++ b/arch/arm/common/pl330.c
@@ -1502,12 +1502,13 @@ int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op)
struct pl330_thread *thrd = ch_id;
struct pl330_dmac *pl330;
unsigned long flags;
- int ret = 0, active = thrd->req_running;
+ int ret = 0, active;
if (!thrd || thrd->free || thrd->dmac->state == DYING)
return -EINVAL;
pl330 = thrd->dmac;
+ active = thrd->req_running;
spin_lock_irqsave(&pl330->lock, flags);