PRIVATE: HACK: changes req to use midgaurd mali and remove the strides for peach pi and pit.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>

6 files changed, 56 insertions, 30 deletions

diff --git a/drivers/gpu/arm/midgard/Kbuild b/drivers/gpu/arm/midgard/Kbuild
index 1e6510de8616..8e9db9865328 100644
--- a/drivers/gpu/arm/midgard/Kbuild
+++ b/drivers/gpu/arm/midgard/Kbuild
@@ -22,6 +22,7 @@ KBASE_PATH = $(src)
 KBASE_PLATFORM_PATH = $(KBASE_PATH)/platform_dummy
 UMP_PATH = $(src)/../../../base
 EXYNOS_PATH_MACH = $(src)/../../../../arch/arm/mach-exynos/include
+EXYNOS_PATH_MACH_1= $(src)/../../../../../../arch/arm/mach-exynos
 EXYNOS_PATH_PLAT = $(src)/../../../../arch/arm/plat-samsung/include
 
 ifeq ($(CONFIG_MALI_ERROR_INJECTION),y)
@@ -70,7 +71,7 @@ endif
 
 # Use our defines when compiling
 ccflags-y += $(DEFINES) -I$(KBASE_PATH)   -I$(KBASE_PLATFORM_PATH) -I$(UMP_PATH)
-subdir-ccflags-y += $(DEFINES) -I$(KBASE_PATH)   -I$(KBASE_PLATFORM_PATH) -I$(OSK_PATH) -I$(UMP_PATH) -I$(EXYNOS_PATH_MACH) -I$(EXYNOS_PATH_PLAT)
+subdir-ccflags-y += $(DEFINES) -I$(KBASE_PATH)   -I$(KBASE_PLATFORM_PATH) -I$(OSK_PATH) -I$(UMP_PATH) -I$(EXYNOS_PATH_MACH) -I$(EXYNOS_PATH_PLAT) -I$(EXYNOS_PATH_1)
 
 SRC := \
 	mali_kbase_device.c \
diff --git a/drivers/gpu/arm/midgard/mali_kbase_core_linux.c b/drivers/gpu/arm/midgard/mali_kbase_core_linux.c
index 8ee5f965931e..1adc91c41240 100644
--- a/drivers/gpu/arm/midgard/mali_kbase_core_linux.c
+++ b/drivers/gpu/arm/midgard/mali_kbase_core_linux.c
@@ -2953,11 +2953,24 @@ static struct platform_driver kbase_platform_driver = {
 };
 
 /*
- * The driver will not provide a shortcut to create the Mali platform device
+ * The deiver will not provide a shortnut to create the Mali platform device
  * anymore when using Device Tree.
  */
 #ifdef CONFIG_OF
-module_platform_driver(kbase_platform_driver);
+//module_platform_driver(kbase_platform_driver);
+
+static int __init kbase_init(void)
+{
+       return platform_driver_register(&kbase_platform_driver);
+}
+late_initcall(kbase_init);
+
+static void __exit kbase_exit(void)
+{
+       platform_driver_unregister(&kbase_platform_driver);
+}
+module_exit(kbase_exit);
+
 #else /* CONFIG_MALI_PLATFORM_FAKE */
 
 extern int kbase_platform_early_init(void);
@@ -2997,7 +3010,7 @@ static void __exit kbase_driver_exit(void)
 #endif
 }
 
-module_init(kbase_driver_init);
+late_initcall(kbase_driver_init);
 module_exit(kbase_driver_exit);
 
 #endif /* CONFIG_OF */
diff --git a/drivers/gpu/arm/midgard/platform/chromebook/mali_kbase_config_chromebook.c b/drivers/gpu/arm/midgard/platform/chromebook/mali_kbase_config_chromebook.c
index 2df7d8f1b82d..0b84b01a42f1 100644
--- a/drivers/gpu/arm/midgard/platform/chromebook/mali_kbase_config_chromebook.c
+++ b/drivers/gpu/arm/midgard/platform/chromebook/mali_kbase_config_chromebook.c
@@ -38,7 +38,6 @@
 #include <mach/regs-clock.h>
 //#include <mach/pmu.h>
 #include <mach/common.h>
-#include <mach/regs-pmu.h>
 #include <asm/delay.h>
 #include <mach/map.h>
 #include <generated/autoconf.h>
@@ -63,6 +62,8 @@
 #include <mali_kbase_defs.h>
 
 #include "mali_linux_dvfs_trace.h"
+extern void __iomem *pmu_base_addr;
+//#include "arch/arm/mach-exynos/common.h"
 
 #define MALI_DVFS_DEBUG 0
 #define MALI_DVFS_STEP 8
@@ -86,6 +87,8 @@
 #define CONFIG_MIDGARD_HWVER_R0P0 1
 #define G3D_ASV_VOL_OFFSET	25000
 
+#define pmu_raw_writel(val, offset) \
+		__raw_writel(val, pmu_base_addr + offset)
 struct regulator *kbase_platform_get_regulator(void);
 int kbase_platform_regulator_init(void);
 int kbase_platform_regulator_disable(void);
@@ -99,6 +102,12 @@ static void kbase_platform_dvfs_set_level(kbase_device *kbdev, int level);
 static int kbase_platform_dvfs_get_level(int freq);
 #endif
 
+#define EXYNOS5_G3D_CONFIGURATION 0x4060
+#define EXYNOS5_G3D_STATUS 0x4064
+
+#define EXYNOS5420_G3D_CONFIGURATION 0x4060
+#define EXYNOS5420_G3D_STATUS 0x4064
+
 #if defined(CONFIG_MALI_MIDGARD_DVFS) || defined(CONFIG_MALI_MIDGARD_DEBUG_SYS)
 struct mali_dvfs_info {
 	unsigned int voltage;
@@ -539,12 +548,12 @@ static int kbase_platform_power_clock_init(kbase_device *kbdev)
 
 	/* Turn on G3D power */
 	if (soc_is_exynos5250()) {
-		g3d_status_reg = EXYNOS5_G3D_STATUS;
-		__raw_writel(0x7, EXYNOS5_G3D_CONFIGURATION);
+		g3d_status_reg = pmu_base_addr + EXYNOS5_G3D_STATUS;
+		pmu_raw_writel(0x7, EXYNOS5_G3D_CONFIGURATION);
 	}
 	else if (soc_is_exynos5420() || soc_is_exynos5800()) {
-		g3d_status_reg = EXYNOS5420_G3D_STATUS;
-		__raw_writel(0x7, EXYNOS5420_G3D_CONFIGURATION);
+		g3d_status_reg = pmu_base_addr + EXYNOS5420_G3D_STATUS;
+		pmu_raw_writel(0x7, EXYNOS5_G3D_CONFIGURATION);
 	}
 
 	/* Wait for G3D power stability for 1ms */
@@ -677,12 +686,12 @@ static int kbase_platform_power_on(void)
 
 	/* Turn on G3D power */
 	if (soc_is_exynos5250()) {
-		g3d_status_reg = EXYNOS5_G3D_STATUS;
-		__raw_writel(0x7, EXYNOS5_G3D_CONFIGURATION);
+		g3d_status_reg = pmu_base_addr + EXYNOS5_G3D_STATUS;
+		pmu_raw_writel(0x7, EXYNOS5_G3D_CONFIGURATION);
 	}
 	else if (soc_is_exynos5420() || soc_is_exynos5800()) {
-		g3d_status_reg = EXYNOS5420_G3D_STATUS;
-		__raw_writel(0x7, EXYNOS5420_G3D_CONFIGURATION);
+		g3d_status_reg = pmu_base_addr + EXYNOS5420_G3D_STATUS;
+		pmu_raw_writel(0x7, EXYNOS5420_G3D_CONFIGURATION);
 	}
 
 	/* Wait for G3D power stability */
@@ -710,12 +719,12 @@ static int kbase_platform_power_off(void)
 
 	/* Turn off G3D  */
 	if (soc_is_exynos5250()) {
-		g3d_status_reg = EXYNOS5_G3D_STATUS;
-		__raw_writel(0x0, EXYNOS5_G3D_CONFIGURATION);
+		g3d_status_reg = pmu_base_addr + EXYNOS5_G3D_STATUS;
+		pmu_raw_writel(0x0, EXYNOS5_G3D_CONFIGURATION);
 	}
 	else if (soc_is_exynos5420() || soc_is_exynos5800()) {
-		g3d_status_reg = EXYNOS5420_G3D_STATUS;
-		__raw_writel(0x0, EXYNOS5420_G3D_CONFIGURATION);
+		g3d_status_reg = pmu_base_addr + EXYNOS5420_G3D_STATUS;
+		pmu_raw_writel(0x0, EXYNOS5420_G3D_CONFIGURATION);
 	}
 
 	/* Wait for G3D power stability */
@@ -978,14 +987,14 @@ static void set_clkout_for_3d(void)
 	tmp = 0x0;
 	tmp |= 0x1000B; /* ACLK_400 selected */
 	tmp |= 9 << 8;  /* divided by (9 + 1) */
-	__raw_writel(tmp, /*EXYNOS5_CLKOUT_CMU_TOP*/EXYNOS_CLKREG(0x10A00));
+	__raw_writel(tmp, /*EXYNOS5_CLKOUT_CMU_TOP*/pmu_base_addr + (0x10A00));
 
 #ifdef PMU_XCLKOUT_SET
 	exynos5_pmu_xclkout_set(1, XCLKOUT_CMU_TOP);
 #else /* PMU_XCLKOUT_SET */
 	tmp = 0x0;
 	tmp |= 7 << 8; /* CLKOUT_CMU_TOP selected */
-	__raw_writel(tmp, /*S5P_PMU_DEBUG*/S5P_PMUREG(0x0A00));
+	__raw_writel(tmp, /*S5P_PMU_DEBUG*/pmu_base_addr + (0x0A00));
 #endif /* PMU_XCLKOUT_SET */
 }
 
@@ -1589,7 +1598,7 @@ int kbase_platform_regulator_init(void)
 	{
 		kbase_platform_regulator_disable();
 		printk("[kbase_platform_regulator_init] failed to set mali t6xx operating voltage [%d]\n", mali_gpu_vol);
-		return -1;
+		//return -1;
 	}
 #endif /* CONFIG_REGULATOR */
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h
index d22e640f59a0..f031e7e62997 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h
@@ -110,7 +110,7 @@ struct exynos_drm_overlay {
 	unsigned int refresh;
 	unsigned int scan_flag;
 	unsigned int bpp;
-	unsigned int pitch;
+	unsigned int fb_pitch;
 	uint32_t pixel_format;
 	dma_addr_t dma_addr[MAX_FB_BUFFER];
 	int zpos;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 085b066a9993..ddac6c92ebd6 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -136,6 +136,7 @@ struct fimd_win_data {
 	unsigned int		ovl_height;
 	unsigned int		fb_width;
 	unsigned int		fb_height;
+	unsigned int		fb_pitch;
 	unsigned int		bpp;
 	unsigned int		pixel_format;
 	dma_addr_t		dma_addr;
@@ -483,9 +484,10 @@ static void fimd_win_mode_set(struct exynos_drm_manager *mgr,
 		return;
 
 	offset = overlay->fb_x * (overlay->bpp >> 3);
-	offset += overlay->fb_y * overlay->pitch;
+	offset += overlay->fb_y * overlay->fb_pitch;
 
-	DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
+	DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n",
+		offset, overlay->fb_pitch);
 
 	win_data = &ctx->win_data[win];
 
@@ -495,12 +497,13 @@ static void fimd_win_mode_set(struct exynos_drm_manager *mgr,
 	win_data->ovl_height = overlay->crtc_height;
 	win_data->fb_width = overlay->fb_width;
 	win_data->fb_height = overlay->fb_height;
+	win_data->fb_pitch = overlay->fb_pitch;
 	win_data->dma_addr = overlay->dma_addr[0] + offset;
 	win_data->bpp = overlay->bpp;
 	win_data->pixel_format = overlay->pixel_format;
-	win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
-				(overlay->bpp >> 3);
-	win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
+	win_data->buf_offsize = overlay->fb_pitch -
+		(overlay->fb_width * (overlay->bpp >> 3));
+	win_data->line_size = overlay->fb_width * (overlay->bpp >> 3);
 
 	DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
 			win_data->offset_x, win_data->offset_y);
@@ -665,7 +668,7 @@ static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos)
 	writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 
 	/* buffer end address */
-	size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
+	size = win_data->fb_height * win_data->fb_pitch;
 	val = (unsigned long)(win_data->dma_addr + size);
 	writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index c7045a663763..42288b618fa7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -115,12 +115,12 @@ int exynos_plane_mode_set(struct drm_plane *plane, struct drm_crtc *crtc,
 	/* set drm framebuffer data. */
 	overlay->fb_x = src_x;
 	overlay->fb_y = src_y;
-	overlay->fb_width = fb->width;
-	overlay->fb_height = fb->height;
+	overlay->fb_width = min(fb->width, actual_w);
+	overlay->fb_height = min(fb->height, actual_h);
+	overlay->fb_pitch = fb->pitches[0];
 	overlay->src_width = src_w;
 	overlay->src_height = src_h;
 	overlay->bpp = fb->bits_per_pixel;
-	overlay->pitch = fb->pitches[0];
 	overlay->pixel_format = fb->pixel_format;
 
 	/* set overlay range to be displayed. */