arm: perf: Directly handle SMP platforms with one SPIhacking/perf

Some ARM platforms mux the PMU interrupt of every core into a single
SPI. On such platforms if the PMU of any core except 0 raises an interrupt
then it cannot be serviced and, eventually, the spurious irq detection
will forcefully disable the interrupt.

On these SoCs it is not possible to determine which core raised the
interrupt. However we can workaround this by queuing irqwork on the other
cores whenever the primary interrupt handler is unable to service the
interrupt.

The u8500 already works around this by dynamically altering the affinity
of the PMU interrupt. This workaround logic is no longer required so the
original code is removed as is the hook which it relied on.

Tested on imx6q (which has fours cores/PMUs all muxed to a single SPI).

Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>

1 files changed, 94 insertions, 0 deletions

diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index eb2c4d55666b..e7153dc3b489 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -88,6 +88,75 @@ static void cpu_pmu_disable_percpu_irq(void *data)
 	disable_percpu_irq(irq);
 }
 
+/*
+ * Workaround logic that is distributed to all cores if the PMU has only
+ * a single IRQ and the CPU receiving that IRQ cannot handle it. Its
+ * job is to try to service the interrupt on the current CPU. It will
+ * also enable the IRQ again if all the other CPUs have already tried to
+ * service it.
+ */
+static void cpu_pmu_do_percpu_work(struct irq_work *w)
+{
+	struct arm_pmu_work *work = container_of(w, struct arm_pmu_work, work);
+	struct arm_pmu *cpu_pmu = work->arm_pmu;
+
+	atomic_set(&work->ret,
+		   cpu_pmu->handle_irq(cpu_pmu->single_irq, cpu_pmu));
+
+	if (atomic_dec_and_test(&cpu_pmu->remaining_work))
+		enable_irq(cpu_pmu->single_irq);
+}
+
+/*
+ * This callback, which is enabled only on SMP platforms that are
+ * running with a single IRQ, is called when the PMU handler running in
+ * the current CPU cannot service the interrupt.
+ *
+ * It will disable the interrupt and distribute irqwork to all other
+ * processors in the system. Hopefully one of them will clear the
+ * interrupt...
+ */
+static irqreturn_t cpu_pmu_handle_irq_none(struct arm_pmu *cpu_pmu)
+{
+	int num_online = num_online_cpus();
+	irqreturn_t ret = IRQ_NONE;
+	int cpu, cret;
+
+	if (num_online <= 1)
+		return IRQ_NONE;
+
+	disable_irq_nosync(cpu_pmu->single_irq);
+	atomic_add(num_online, &cpu_pmu->remaining_work);
+	smp_mb__after_atomic();
+
+	for_each_online_cpu(cpu) {
+		struct arm_pmu_work *work = per_cpu_ptr(cpu_pmu->work, cpu);
+
+		if (cpu == smp_processor_id())
+			continue;
+
+		/*
+		 * We can be extremely relaxed about memory ordering
+		 * here. All we are doing is gathering information
+		 * about the past to help us give a return value that
+		 * will keep the spurious interrupt detector both happy
+		 * *and* functional. We are not shared so we can
+		 * tolerate the occasional spurious IRQ_HANDLED.
+		 */
+		cret = atomic_read(&work->ret);
+		if (cret != IRQ_NONE)
+			ret = cret;
+
+		if (!irq_work_queue_on(&work->work, cpu))
+			atomic_dec(&cpu_pmu->remaining_work);
+	}
+
+	if (atomic_dec_and_test(&cpu_pmu->remaining_work))
+		enable_irq(cpu_pmu->single_irq);
+
+	return ret;
+}
+
 static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
 {
 	int i, irq, irqs;
@@ -107,6 +176,9 @@ static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
 			if (irq >= 0)
 				free_irq(irq, cpu_pmu);
 		}
+
+		cpu_pmu->handle_irq_none = cpu_pmu_handle_irq_none;
+		free_percpu(cpu_pmu->work);
 	}
 }
 
@@ -162,6 +234,28 @@ static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
 
 			cpumask_set_cpu(i, &cpu_pmu->active_irqs);
 		}
+
+		/*
+		 * If we are running SMP and have only one interrupt source
+		 * then get ready to share that single irq among the cores.
+		 */
+		if (nr_cpu_ids > 1 && irqs == 1) {
+			cpu_pmu->single_irq = platform_get_irq(pmu_device, 0);
+			cpu_pmu->work = alloc_percpu(struct arm_pmu_work);
+			if (!cpu_pmu->work) {
+				pr_err("no memory for shared IRQ workaround\n");
+				return -ENOMEM;
+			}
+
+			for_each_possible_cpu(i) {
+				struct arm_pmu_work *w =
+				    per_cpu_ptr(cpu_pmu->work, i);
+				init_irq_work(&w->work, cpu_pmu_do_percpu_work);
+				w->arm_pmu = cpu_pmu;
+			}
+
+			cpu_pmu->handle_irq_none = cpu_pmu_handle_irq_none;
+		}
 	}
 
 	return 0;