From 7ba3417aff9cf65112ca91753a7ac8cef70430de Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 24 Sep 2014 15:58:30 +0100 Subject: ARM: DT: apq8064: add rpm support This patch adds rpm node to apq8064 dt as rpm would be used by other devices for regulator support. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index b3154c071652..9c2c8e6b21d6 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -3,6 +3,7 @@ #include "skeleton.dtsi" #include #include +#include #include #include @@ -246,6 +247,24 @@ #reset-cells = <1>; }; + apcs: syscon@2011000 { + compatible = "syscon"; + reg = <0x2011000 0x1000>; + }; + + rpm@108000 { + compatible = "qcom,rpm-apq8064"; + reg = <0x108000 0x1000>; + qcom,ipc = <&apcs 0x8 2>; + + interrupts = <0 19 0>, <0 21 0>, <0 22 0>; + interrupt-names = "ack", "err", "wakeup"; + + #address-cells = <1>; + #size-cells = <0>; + + }; + /* Temporary fixed regulator */ vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed"; -- cgit v1.2.3 From fc56035b7d87cbebbb97b5caac2bf3786ce07036 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 24 Sep 2014 16:00:36 +0100 Subject: ARM: DT: apq8064: Add usb host support. This patch adds device tree nodes to support two usb hosts on APQ8064 SOC. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 16 ++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 85 ++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index b396c8311b27..d6036b822eac 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -40,6 +40,22 @@ }; }; + usb3_phy:phy@12520000 { + status = "ok"; + }; + + usb4_phy:phy@12530000 { + status = "ok"; + }; + + usb3: usb@12520000 { + status = "ok"; + }; + + usb4: usb@12530000 { + status = "ok"; + }; + amba { /* eMMC */ sdcc1: sdcc@12400000 { diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 9c2c8e6b21d6..491a136d712c 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -263,6 +263,91 @@ #address-cells = <1>; #size-cells = <0>; + pm8921_s3: pm8921-s3 { + compatible = "qcom,rpm-pm8921-smps"; + reg = ; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + qcom,boot-load = <49360>; + qcom,switch-mode-frequency = <3200000>; + regulator-always-on; + }; + + pm8921_l3: pm8921-l3 { + compatible = "qcom,rpm-pm8921-pldo"; + reg = ; + + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + qcom,boot-load = <50000>; + }; + + pm8921_l23: pm8921-l23 { + compatible = "qcom,rpm-pm8921-pldo"; + reg = ; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + qcom,boot-load = <50000>; + regulator-always-on; + }; + + }; + + usb3_phy:phy@12520000 { + compatible = "qcom,usb-otg-ci"; + reg = <0x12520000 0x400>; + interrupts = <0 188 0>; + status = "disabled"; + dr_mode = "host"; + + clocks = <&gcc USB_HS3_XCVR_CLK>, + <&gcc USB_HS3_H_CLK>; + clock-names = "core", "iface"; + + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + + resets = <&gcc USB_HS3_RESET>; + reset-names = "link"; + }; + + usb4_phy:phy@12530000 { + compatible = "qcom,usb-otg-ci"; + reg = <0x12530000 0x400>; + interrupts = <0 215 0>; + status = "disabled"; + dr_mode = "host"; + + clocks = <&gcc USB_HS4_XCVR_CLK>, + <&gcc USB_HS4_H_CLK>; + clock-names = "core", "iface"; + + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + + resets = <&gcc USB_HS4_RESET>; + reset-names = "link"; + }; + + usb3: usb@12520000 { + compatible = "qcom,ehci-host"; + reg = <0x12520000 0x400>; + interrupts = <0 188 0>; + status = "disabled"; + usb-phy = <&usb3_phy>; + }; + + usb4: usb@12530000 { + compatible = "qcom,ehci-host"; + reg = <0x12530000 0x400>; + interrupts = <0 215 0>; + status = "disabled"; + usb-phy = <&usb4_phy>; }; /* Temporary fixed regulator */ -- cgit v1.2.3 From 7929927b3873de0321161555b0f6306d7a216717 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Thu, 19 Jun 2014 13:16:48 +0100 Subject: ARM: DT: apq8064: Add USB OTG support This patch adds USB OTG support on USB1 of APQ8064 SOC. Tested on IFC6410 with ethernet gadget. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 14 +++++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 47 ++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index d6036b822eac..f41fb39fb57d 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -40,6 +40,11 @@ }; }; + /* OTG */ + usb1_phy:phy@12500000 { + status = "ok"; + }; + usb3_phy:phy@12520000 { status = "ok"; }; @@ -48,6 +53,15 @@ status = "ok"; }; + gadget1:gadget@12500000 { + status = "ok"; + }; + + /* OTG */ + usb1: usb@12500000 { + status = "ok"; + }; + usb3: usb@12520000 { status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 491a136d712c..ce976b1982c4 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -2,6 +2,7 @@ #include "skeleton.dtsi" #include +#include #include #include #include @@ -284,6 +285,16 @@ qcom,boot-load = <50000>; }; + pm8921_l4: pm8921-l4 { + compatible = "qcom,rpm-pm8921-pldo"; + reg = ; + + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + qcom,boot-load = <50000>; + }; + pm8921_l23: pm8921-l23 { compatible = "qcom,rpm-pm8921-pldo"; reg = ; @@ -296,6 +307,25 @@ }; + usb1_phy:phy@12500000 { + compatible = "qcom,usb-otg-ci"; + reg = <0x12500000 0x400>; + interrupts = <0 100 0>; + status = "disabled"; + dr_mode = "host"; + + clocks = <&gcc USB_HS1_XCVR_CLK>, + <&gcc USB_HS1_H_CLK>; + clock-names = "core", "iface"; + + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + + resets = <&gcc USB_HS1_RESET>; + reset-names = "link"; + }; + usb3_phy:phy@12520000 { compatible = "qcom,usb-otg-ci"; reg = <0x12520000 0x400>; @@ -334,6 +364,23 @@ reset-names = "link"; }; + gadget1:gadget@12500000 { + compatible = "qcom,ci-hdrc"; + reg = <0x12500000 0x400>; + status = "disabled"; + dr_mode = "peripheral"; + interrupts = <0 100 0>; + usb-phy = <&usb1_phy>; + }; + + usb1: usb@12500000 { + compatible = "qcom,ehci-host"; + reg = <0x12500000 0x400>; + interrupts = <0 100 0>; + status = "disabled"; + usb-phy = <&usb1_phy>; + }; + usb3: usb@12520000 { compatible = "qcom,ehci-host"; reg = <0x12520000 0x400>; -- cgit v1.2.3 From ea7843db24b018a3479d456098297f3270c80105 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 23 Jun 2014 18:14:38 +0100 Subject: ARM: DT: apq8064: Add SATA controller support. This patch adds AHCI based SATA controller support to APQ8064. Tested on IFC6410 board. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 40 +++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index ce976b1982c4..bb7ef92a4d9e 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -275,6 +275,17 @@ regulator-always-on; }; + pm8921_s4: pm8921-s4 { + compatible = "qcom,rpm-pm8921-smps"; + reg = ; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,boot-load = <200000>; + qcom,switch-mode-frequency = <3200000>; + regulator-always-on; + }; + pm8921_l3: pm8921-l3 { compatible = "qcom,rpm-pm8921-pldo"; reg = ; @@ -397,6 +408,35 @@ usb-phy = <&usb4_phy>; }; + sata_phy0:sata-phy@1b400000{ + compatible = "qcom,apq8064-sata-phy"; + reg = <0x1b400000 0x200>; + reg-names = "phy_mem"; + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + #phy-cells = <0>; + }; + + sata0: sata@29000000 { + compatible = "generic-ahci"; + reg = <0x29000000 0x180>; + interrupts = <0 209 0>; + clocks = <&gcc SFAB_SATA_S_H_CLK>, <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + + clock-names = "slave_iface", "iface", + "bus", "rxoob", + "core_pmalive"; + assigned-clocks = <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy0>; + phy-names = "sata-phy"; + target-supply = <&pm8921_s4>; + }; + /* Temporary fixed regulator */ vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed"; -- cgit v1.2.3 From 289acb0706b8493acabab913e50064e44a108e62 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Wed, 9 Jul 2014 18:08:32 +0100 Subject: ARM: DT: apq8064: add pci support This patch adds PCIE support to APQ8064, tested on IFC6410 board. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 19 ++++++++++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 47 ++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index f41fb39fb57d..1ab6505ee40b 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -1,4 +1,5 @@ #include "qcom-apq8064-v2.0.dtsi" +#include / { model = "Qualcomm APQ8064/IFC6410"; @@ -69,6 +70,24 @@ usb4: usb@12530000 { status = "ok"; }; + + /* on board fixed 3.3v supply */ + v3p3_pcieclk: v3p3-pcieclk { + compatible = "regulator-fixed"; + regulator-name = "PCIE V3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + pci@1b500000 { + status = "ok"; + pcie-clk-supply = <&v3p3_pcieclk>; + avdd-supply = <&pm8921_s3>; + vdd-supply = <&pm8921_lvs6>; + qcom,external-phy-refclk; + reset-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + }; amba { /* eMMC */ diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index bb7ef92a4d9e..cbc5e7114507 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { model = "Qualcomm APQ8064"; @@ -316,8 +317,54 @@ regulator-always-on; }; + + pm8921_lvs6: pm8921-lvs6 { + compatible = "qcom,rpm-pm8921-switch"; + reg = ; + regulator-always-on; + }; + + }; + /* PCIE */ + + pci@1b500000 { + compatible = "qcom,pcie-ipq8064"; + reg = <0x1b500000 0x1000>, <0x1b502000 0x100>, <0x1b600000 0x80>; + reg-names = "base", "elbi", "parf"; + status = "disabled"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + interrupts = <0 35 0x0 + 0 36 0x0 + 0 37 0x0 + 0 38 0x0 + 0 39 0x0 + 0 238 0x0>; + interrupt-names = "irq1", "irq2", "irq3", "irq4", "iqr5", "msi"; + + resets = <&gcc PCIE_ACLK_RESET>, + <&gcc PCIE_HCLK_RESET>, + <&gcc PCIE_POR_RESET>, + <&gcc PCIE_PCI_RESET>, + <&gcc PCIE_PHY_RESET>; + reset-names = "axi", "ahb", "por", "pci", "phy"; + + clocks = <&gcc PCIE_A_CLK>, + <&gcc PCIE_H_CLK>, + <&gcc PCIE_PHY_REF_CLK>; + clock-names = "core", "iface", "phy"; + + ranges = <0x00000000 0 0 0x0ff00000 0 0x00100000 /* configuration space */ + 0x81000000 0 0 0x0fe00000 0 0x00100000 /* downstream I/O */ + 0x82000000 0 0 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ + + }; + + + usb1_phy:phy@12500000 { compatible = "qcom,usb-otg-ci"; reg = <0x12500000 0x400>; -- cgit v1.2.3 From 1fe73f0bb7e482b4bb483c806dd864bd41dd7212 Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 18 Aug 2014 07:41:09 +0100 Subject: ARM: DT: apq8064: Add pmic gpio node This patch adds pmic gpio node to the device tree, this node is necessary for devices like wlan to control reset gpio. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index cbc5e7114507..c609df417469 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -8,7 +8,6 @@ #include #include #include - / { model = "Qualcomm APQ8064"; compatible = "qcom,apq8064"; @@ -233,6 +232,40 @@ compatible = "qcom,ssbi"; reg = <0x00500000 0x1000>; qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic@0 { + compatible = "qcom,pm8921"; + interrupt-parent = <&tlmm_pinmux>; + interrupts = <74 8>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + pm8921_gpio: gpio@150 { + + compatible = "qcom,pm8921-gpio"; + reg = <0x150>; + interrupts = <192 1>, <193 1>, <194 1>, + <195 1>, <196 1>, <197 1>, + <198 1>, <199 1>, <200 1>, + <201 1>, <202 1>, <203 1>, + <204 1>, <205 1>, <206 1>, + <207 1>, <208 1>, <209 1>, + <210 1>, <211 1>, <212 1>, + <213 1>, <214 1>, <215 1>, + <216 1>, <217 1>, <218 1>, + <219 1>, <220 1>, <221 1>, + <222 1>, <223 1>, <224 1>, + <225 1>, <226 1>, <227 1>, + <228 1>, <229 1>, <230 1>, + <231 1>, <232 1>, <233 1>, + <234 1>, <235 1>; + + gpio-controller; + #gpio-cells = <2>; + + }; + }; }; gcc: clock-controller@900000 { -- cgit v1.2.3 From 229ca64dcffef80861a0106cf60f04e25064077a Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Mon, 18 Aug 2014 07:44:09 +0100 Subject: ARM: DT: ifc6410: add wlan node with reset line. This patch adds wlan node with platform specfic reset gpio line. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 5 +++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 15 ++++++++++++--- 2 files changed, 17 insertions(+), 3 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 1ab6505ee40b..dbb33cb3df82 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -89,6 +89,11 @@ reset-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; }; + wlan0 { + compatible = "atheros,ath6kl"; + reset-gpio = <&pm8921_gpio 42 GPIO_ACTIVE_LOW>; + }; + amba { /* eMMC */ sdcc1: sdcc@12400000 { diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index c609df417469..f9a16ad1ffa6 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -7,7 +7,7 @@ #include #include #include -#include +#include / { model = "Qualcomm APQ8064"; compatible = "qcom,apq8064"; @@ -242,7 +242,6 @@ #address-cells = <1>; #size-cells = <0>; pm8921_gpio: gpio@150 { - compatible = "qcom,pm8921-gpio"; reg = <0x150>; interrupts = <192 1>, <193 1>, <194 1>, @@ -263,7 +262,17 @@ gpio-controller; #gpio-cells = <2>; - + pinctrl-names = "default"; + pinctrl-0 = <&wlan_default_gpios>; + + wlan_default_gpios: wlan-gpios { + pios { + pins = "gpio43"; + function = "normal"; + bias-disable; + power-source = ; + }; + }; }; }; }; -- cgit v1.2.3 From 3610186d568662d5abffd4c7277403d24ead5781 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 8 Sep 2014 17:40:59 +0100 Subject: ARM: DT: APQ8064: Add MDP support This patch adds MDP node to APQ8064 dt. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 108 ++++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index f9a16ad1ffa6..8af894f2a99c 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1,6 +1,7 @@ /dts-v1/; #include "skeleton.dtsi" +#include #include #include #include @@ -94,6 +95,20 @@ }; }; + hdmi_pinctrl: hdmi-pinctrl { + mux1 { + pins = "gpio69", "gpio70", "gpio71"; + function = "hdmi"; + bias-pull-up; + drive-strength = <2>; + }; + mux2 { + pins = "gpio72"; + function = "hdmi"; + bias-pull-down; + drive-strength = <16>; + }; + }; ps_hold: ps_hold { mux { pins = "gpio78"; @@ -228,6 +243,18 @@ }; }; + ext_3p3v: regulator-fixed@1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ext_3p3v"; + regulator-type = "voltage"; + startup-delay-us = <0>; + gpio = <&tlmm_pinmux 77 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + qcom,ssbi@500000 { compatible = "qcom,ssbi"; reg = <0x00500000 0x1000>; @@ -366,6 +393,12 @@ regulator-always-on; }; + pm8921_hdmi_mvs: pm8921-hdmi-mvs { + compatible = "qcom,rpm-pm8921-switch"; + reg = ; + regulator-always-on; + bias-pull-down; + }; }; @@ -629,5 +662,80 @@ pinctrl-0 = <&sdc4_gpios>; }; }; + + hdmi: qcom,hdmi-tx@4a00000 { + compatible = "qcom,hdmi-tx-8960"; + reg-names = "core_physical"; + reg = <0x04a00000 0x1000>; + interrupts = ; + clock-names = + "core_clk", + "master_iface_clk", + "slave_iface_clk"; + clocks = + <&mmcc HDMI_APP_CLK>, + <&mmcc HDMI_M_AHB_CLK>, + <&mmcc HDMI_S_AHB_CLK>; + qcom,hdmi-tx-ddc-clk = <&tlmm_pinmux 70 GPIO_ACTIVE_HIGH>; + qcom,hdmi-tx-ddc-data = <&tlmm_pinmux 71 GPIO_ACTIVE_HIGH>; + qcom,hdmi-tx-hpd = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; + core-vdda-supply = <&pm8921_hdmi_mvs>; + hdmi-mux-supply = <&ext_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pinctrl>; + }; + + gpu: qcom,adreno-3xx@4300000 { + compatible = "qcom,adreno-3xx"; + reg = <0x04300000 0x20000>; + reg-names = "kgsl_3d0_reg_memory"; + interrupts = ; + interrupt-names = "kgsl_3d0_irq"; + clock-names = + "core_clk", + "iface_clk", + "mem_clk", + "mem_iface_clk"; + clocks = + <&mmcc GFX3D_CLK>, + <&mmcc GFX3D_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>, + <&mmcc MMSS_IMEM_AHB_CLK>; + qcom,chipid = <0x03020002>; + qcom,gpu-pwrlevels { + compatible = "qcom,gpu-pwrlevels"; + qcom,gpu-pwrlevel@0 { + qcom,gpu-freq = <450000000>; + }; + qcom,gpu-pwrlevel@1 { + qcom,gpu-freq = <27000000>; + }; + }; + }; + + mdp: qcom,mdp@5100000 { + compatible = "qcom,mdp"; + reg = <0x05100000 0xf0000>; + interrupts = ; + connectors = <&hdmi>; + gpus = <&gpu>; + clock-names = + "core_clk", + "iface_clk", + "lut_clk", + "src_clk", + "hdmi_clk", + "mdp_clk", + "mdp_axi_clk"; + clocks = + <&mmcc MDP_CLK>, + <&mmcc MDP_AHB_CLK>, + <&mmcc MDP_LUT_CLK>, + <&mmcc TV_SRC>, + <&mmcc HDMI_TV_CLK>, + <&mmcc MDP_TV_CLK>, + <&mmcc MDP_AXI_CLK>; +// vdd-supply = <&footswitch_mdp>; + }; }; }; -- cgit v1.2.3 From b32972963cf5ac5d5f3f1fdb49fbae94f4e99818 Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Wed, 9 Jul 2014 22:07:15 -0400 Subject: WIP: ARM: DT: APQ8064: Add iommu --- arch/arm/boot/dts/qcom-apq8064.dtsi | 92 +++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 8af894f2a99c..938067802df4 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -687,6 +687,7 @@ gpu: qcom,adreno-3xx@4300000 { compatible = "qcom,adreno-3xx"; + #stream-id-cells = <16>; reg = <0x04300000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; interrupts = ; @@ -715,6 +716,7 @@ mdp: qcom,mdp@5100000 { compatible = "qcom,mdp"; + #stream-id-cells = <2>; reg = <0x05100000 0xf0000>; interrupts = ; connectors = <&hdmi>; @@ -737,5 +739,95 @@ <&mmcc MDP_AXI_CLK>; // vdd-supply = <&footswitch_mdp>; }; + + mdp_port0: qcom,iommu@7500000 { + compatible = "qcom,iommu-v0"; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg-names = "physbase"; + reg = <0x07500000 0x100000>; + interrupt-names = + "secure_irq", + "nonsecure_irq"; + interrupts = + , + ; + ncb = <2>; + mmu-masters = <&mdp 0 2>; + }; + + mdp_port1: qcom,iommu@7600000 { + compatible = "qcom,iommu"; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc MDP_AXI_CLK>; + reg-names = "physbase"; + reg = <0x07600000 0x100000>; + interrupt-names = + "secure_irq", + "nonsecure_irq"; + interrupts = + , + ; + ncb = <2>; + mmu-masters = <&mdp 0 2>; + }; + + gfx3d: qcom,iommu@7c00000 { + compatible = "qcom,iommu-v0"; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg-names = "physbase"; + reg = <0x07c00000 0x100000>; + interrupt-names = + "secure_irq", + "nonsecure_irq"; + interrupts = + , + ; + ncb = <3>; + ttbr-split = <1>; + mmu-masters = + /* gfx3d_user: */ + <&gpu 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>, + /* gfx3d_priv: */ + <&gpu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; + }; + + gfx3d1: qcom,iommu@7d00000 { + compatible = "qcom,iommu-v0"; + clock-names = + "smmu_pclk", + "iommu_clk"; + clocks = + <&mmcc SMMU_AHB_CLK>, + <&mmcc GFX3D_AXI_CLK>; + reg-names = "physbase"; + reg = <0x07d00000 0x100000>; + interrupt-names = + "secure_irq", + "nonsecure_irq"; + interrupts = + , + ; + ncb = <3>; + ttbr-split = <1>; + mmu-masters = + /* gfx3d_user: */ + <&gpu 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>, + /* gfx3d_priv: */ + <&gpu 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; + }; }; }; -- cgit v1.2.3 From 17d2825fb14f6a6c77c2a17f188ba8d338753c5d Mon Sep 17 00:00:00 2001 From: Rob Clark Date: Mon, 8 Sep 2014 17:47:25 +0100 Subject: WIP: ARM: DT: ifc6410 : add lvds panel Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/qcom-apq8064.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 938067802df4..bf4f13786dcf 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -356,6 +356,17 @@ regulator-always-on; }; + pm8921_l2: pm8921-l2 { + compatible = "qcom,rpm-pm8921-pldo"; + reg = ; + +// ??? + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; +// qcom,boot-load = <50000>; + }; + pm8921_l3: pm8921-l3 { compatible = "qcom,rpm-pm8921-pldo"; reg = ; @@ -393,6 +404,12 @@ regulator-always-on; }; + pm8921_lvs7: pm8921-lvs7 { + compatible = "qcom,rpm-pm8921-switch"; + reg = ; + regulator-always-on; + }; + pm8921_hdmi_mvs: pm8921-hdmi-mvs { compatible = "qcom,rpm-pm8921-switch"; reg = ; @@ -714,6 +731,12 @@ }; }; + panel: auo,b101xtn01 { + compatible = "auo,b101xtn01"; + // lcd1_pwr_en_n: + enable-gpio = <&tlmm_pinmux 36 GPIO_ACTIVE_HIGH>; + }; + mdp: qcom,mdp@5100000 { compatible = "qcom,mdp"; #stream-id-cells = <2>; @@ -721,6 +744,7 @@ interrupts = ; connectors = <&hdmi>; gpus = <&gpu>; + qcom,lvds-panel = <&panel>; clock-names = "core_clk", "iface_clk", @@ -738,6 +762,9 @@ <&mmcc MDP_TV_CLK>, <&mmcc MDP_AXI_CLK>; // vdd-supply = <&footswitch_mdp>; + lvds-vccs-3p3v-supply = <&ext_3p3v>; + lvds-pll-vdda-supply = <&pm8921_l2>; + lvds-vdda-supply = <&pm8921_lvs7>; }; mdp_port0: qcom,iommu@7500000 { -- cgit v1.2.3 From ae5c24b2de55b818350b7e1ce1e10aed39245fbb Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 5 Sep 2014 15:47:36 -0700 Subject: ARM: dts: qcom: Add necessary DT data for Krait cpufreq Add the necessary DT nodes and data so we can probe the cpufreq driver on MSM devices with Krait CPUs. Signed-off-by: Stephen Boyd --- arch/arm/boot/dts/qcom-apq8064.dtsi | 230 ++++++++++++++++++++++++++ arch/arm/boot/dts/qcom-msm8960.dtsi | 49 ++++++ arch/arm/boot/dts/qcom-msm8974.dtsi | 311 +++++++++++++++++++++++++++++++++++- 3 files changed, 586 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index bf4f13786dcf..158fdb4fb694 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -26,6 +26,9 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + clocks = <&kraitcc 0>; + clock-names = "cpu"; + clock-latency = <100000>; }; cpu@1 { @@ -36,6 +39,9 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + clocks = <&kraitcc 1>; + clock-names = "cpu"; + clock-latency = <100000>; }; cpu@2 { @@ -46,6 +52,9 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + clocks = <&kraitcc 2>; + clock-names = "cpu"; + clock-latency = <100000>; }; cpu@3 { @@ -56,6 +65,9 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + clocks = <&kraitcc 3>; + clock-names = "cpu"; + clock-latency = <100000>; }; L2: l2-cache { @@ -69,6 +81,214 @@ interrupts = <1 10 0x304>; }; + qcom,pvs { + qcom,pvs-format-a; + qcom,speed0-pvs0-bin-v0 = + < 384000000 950000 >, + < 486000000 975000 >, + < 594000000 1000000 >, + < 702000000 1025000 >, + < 810000000 1075000 >, + < 918000000 1100000 >; + + qcom,speed0-pvs1-bin-v0 = + < 384000000 900000 >, + < 486000000 925000 >, + < 594000000 950000 >, + < 702000000 975000 >, + < 810000000 1025000 >, + < 918000000 1050000 >; + + qcom,speed0-pvs3-bin-v0 = + < 384000000 850000 >, + < 486000000 875000 >, + < 594000000 900000 >, + < 702000000 925000 >, + < 810000000 975000 >, + < 918000000 1000000 >; + + qcom,speed0-pvs4-bin-v0 = + < 384000000 850000 >, + < 486000000 875000 >, + < 594000000 900000 >, + < 702000000 925000 >, + < 810000000 962500 >, + < 918000000 975000 >; + + qcom,speed1-pvs0-bin-v0 = + < 384000000 950000 >, + < 486000000 950000 >, + < 594000000 950000 >, + < 702000000 962500 >, + < 810000000 1000000 >, + < 918000000 1025000 >; + + qcom,speed1-pvs1-bin-v0 = + < 384000000 950000 >, + < 486000000 950000 >, + < 594000000 950000 >, + < 702000000 962500 >, + < 810000000 975000 >, + < 918000000 1000000 >; + + qcom,speed1-pvs2-bin-v0 = + < 384000000 925000 >, + < 486000000 925000 >, + < 594000000 925000 >, + < 702000000 925000 >, + < 810000000 937500 >, + < 918000000 950000 >; + + qcom,speed1-pvs3-bin-v0 = + < 384000000 900000 >, + < 486000000 900000 >, + < 594000000 900000 >, + < 702000000 900000 >, + < 810000000 900000 >, + < 918000000 925000 >; + + qcom,speed1-pvs4-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed1-pvs5-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed1-pvs6-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed2-pvs0-bin-v0 = + < 384000000 950000 >, + < 486000000 950000 >, + < 594000000 950000 >, + < 702000000 950000 >, + < 810000000 962500 >, + < 918000000 975000 >; + + qcom,speed2-pvs1-bin-v0 = + < 384000000 925000 >, + < 486000000 925000 >, + < 594000000 925000 >, + < 702000000 925000 >, + < 810000000 937500 >, + < 918000000 950000 >; + + qcom,speed2-pvs2-bin-v0 = + < 384000000 900000 >, + < 486000000 900000 >, + < 594000000 900000 >, + < 702000000 900000 >, + < 810000000 912500 >, + < 918000000 925000 >; + + qcom,speed2-pvs3-bin-v0 = + < 384000000 900000 >, + < 486000000 900000 >, + < 594000000 900000 >, + < 702000000 900000 >, + < 810000000 900000 >, + < 918000000 912500 >; + + qcom,speed2-pvs4-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed2-pvs5-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed2-pvs6-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed14-pvs0-bin-v0 = + < 384000000 950000 >, + < 486000000 950000 >, + < 594000000 950000 >, + < 702000000 962500 >, + < 810000000 1000000 >, + < 918000000 1025000 >; + + qcom,speed14-pvs1-bin-v0 = + < 384000000 950000 >, + < 486000000 950000 >, + < 594000000 950000 >, + < 702000000 962500 >, + < 810000000 975000 >, + < 918000000 1000000 >; + + qcom,speed14-pvs2-bin-v0 = + < 384000000 925000 >, + < 486000000 925000 >, + < 594000000 925000 >, + < 702000000 925000 >, + < 810000000 937500 >, + < 918000000 950000 >; + + qcom,speed14-pvs3-bin-v0 = + < 384000000 900000 >, + < 486000000 900000 >, + < 594000000 900000 >, + < 702000000 900000 >, + < 810000000 900000 >, + < 918000000 925000 >; + + qcom,speed14-pvs4-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed14-pvs5-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + + qcom,speed14-pvs6-bin-v0 = + < 384000000 875000 >, + < 486000000 875000 >, + < 594000000 875000 >, + < 702000000 875000 >, + < 810000000 887500 >, + < 918000000 900000 >; + }; + + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + #clock-cells = <1>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -139,21 +359,31 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; }; acc2: clock-controller@20a8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu2_aux"; }; acc3: clock-controller@20b8000 { compatible = "qcom,kpss-acc-v1"; reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu3_aux"; + }; + + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clock-output-names = "acpu_l2_aux"; }; saw0: regulator@2089000 { diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index e1b0d5cd9e3c..ef89daf7a258 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -24,6 +24,10 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + clocks = <&kraitcc 0>; + clock-names = "cpu"; + clock-latency = <100000>; + }; cpu@1 { @@ -34,6 +38,10 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + clocks = <&kraitcc 1>; + clock-names = "cpu"; + clock-latency = <100000>; + }; L2: l2-cache { @@ -48,6 +56,39 @@ qcom,no-pc-write; }; + qcom,pvs { + qcom,pvs-format-a; + /* Hz uV */ + qcom,speed0-pvs0-bin-v0 = + < 384000000 950000 >, + < 486000000 975000 >, + < 594000000 1000000 >, + < 702000000 1025000 >, + < 810000000 1075000 >, + < 918000000 1100000 >; + + qcom,speed0-pvs1-bin-v0 = + < 384000000 900000 >, + < 486000000 925000 >, + < 594000000 950000 >, + < 702000000 975000 >, + < 810000000 1025000 >, + < 918000000 1050000 >; + + qcom,speed0-pvs3-bin-v0 = + < 384000000 850000 >, + < 486000000 875000 >, + < 594000000 900000 >, + < 702000000 925000 >, + < 810000000 975000 >, + < 918000000 1000000 >; + }; + + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + #clock-cells = <1>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -101,11 +142,19 @@ acc0: clock-controller@2088000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu0_aux"; }; acc1: clock-controller@2098000 { compatible = "qcom,kpss-acc-v1"; reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + clock-output-names = "acpu1_aux"; + }; + + l2cc: clock-controller@2011000 { + compatible = "qcom,kpss-gcc"; + reg = <0x2011000 0x1000>; + clock-output-names = "acpu_l2_aux"; }; saw0: regulator@2089000 { diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index e265ec16a787..45ff96d74079 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -14,40 +14,52 @@ #size-cells = <0>; interrupts = <1 9 0xf04>; - cpu@0 { + cpu0: cpu@0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; qcom,acc = <&acc0>; + clocks = <&kraitcc 0>; + clock-names = "cpu"; + clock-latency = <100000>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; qcom,acc = <&acc1>; + clocks = <&kraitcc 1>; + clock-names = "cpu"; + clock-latency = <100000>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; qcom,acc = <&acc2>; + clocks = <&kraitcc 2>; + clock-names = "cpu"; + clock-latency = <100000>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; qcom,acc = <&acc3>; + clocks = <&kraitcc 3>; + clock-names = "cpu"; + clock-latency = <100000>; }; L2: l2-cache { @@ -71,6 +83,267 @@ clock-frequency = <19200000>; }; + qcom,pvs { + qcom,pvs-format-b; + /* Hz uV ua */ + qcom,speed0-pvs0-bin-v0 = + < 300000000 815000 73 >, + < 345600000 825000 85 >, + < 422400000 835000 104 >, + < 499200000 845000 124 >, + < 576000000 855000 144 >, + < 652800000 865000 165 >, + < 729600000 875000 186 >, + < 806400000 890000 208 >, + < 883200000 900000 229 >, + < 960000000 915000 252 >; + + qcom,speed0-pvs1-bin-v0 = + < 300000000 800000 73 >, + < 345600000 810000 85 >, + < 422400000 820000 104 >, + < 499200000 830000 124 >, + < 576000000 840000 144 >, + < 652800000 850000 165 >, + < 729600000 860000 186 >, + < 806400000 875000 208 >, + < 883200000 885000 229 >, + < 960000000 895000 252 >; + + qcom,speed0-pvs2-bin-v0 = + < 300000000 785000 73 >, + < 345600000 795000 85 >, + < 422400000 805000 104 >, + < 499200000 815000 124 >, + < 576000000 825000 144 >, + < 652800000 835000 165 >, + < 729600000 845000 186 >, + < 806400000 855000 208 >, + < 883200000 865000 229 >, + < 960000000 875000 252 >; + + qcom,speed0-pvs3-bin-v0 = + < 300000000 775000 73 >, + < 345600000 780000 85 >, + < 422400000 790000 104 >, + < 499200000 800000 124 >, + < 576000000 810000 144 >, + < 652800000 820000 165 >, + < 729600000 830000 186 >, + < 806400000 840000 208 >, + < 883200000 850000 229 >, + < 960000000 860000 252 >; + + qcom,speed0-pvs4-bin-v0 = + < 300000000 775000 73 >, + < 345600000 775000 85 >, + < 422400000 780000 104 >, + < 499200000 790000 124 >, + < 576000000 800000 144 >, + < 652800000 810000 165 >, + < 729600000 820000 186 >, + < 806400000 830000 208 >, + < 883200000 840000 229 >, + < 960000000 850000 252 >; + + qcom,speed0-pvs5-bin-v0 = + < 300000000 750000 73 >, + < 345600000 760000 85 >, + < 422400000 770000 104 >, + < 499200000 780000 124 >, + < 576000000 790000 144 >, + < 652800000 800000 165 >, + < 729600000 810000 186 >, + < 806400000 820000 208 >, + < 883200000 830000 229 >, + < 960000000 840000 252 >; + + qcom,speed0-pvs6-bin-v0 = + < 300000000 750000 73 >, + < 345600000 750000 85 >, + < 422400000 760000 104 >, + < 499200000 770000 124 >, + < 576000000 780000 144 >, + < 652800000 790000 165 >, + < 729600000 800000 186 >, + < 806400000 810000 208 >, + < 883200000 820000 229 >, + < 960000000 830000 252 >; + + qcom,speed2-pvs0-bin-v0 = + < 300000000 800000 72 >, + < 345600000 800000 83 >, + < 422400000 805000 102 >, + < 499200000 815000 121 >, + < 576000000 825000 141 >, + < 652800000 835000 161 >, + < 729600000 845000 181 >, + < 806400000 855000 202 >, + < 883200000 865000 223 >, + < 960000000 875000 245 >; + + qcom,speed2-pvs1-bin-v0 = + < 300000000 800000 72 >, + < 345600000 800000 83 >, + < 422400000 800000 102 >, + < 499200000 800000 121 >, + < 576000000 810000 141 >, + < 652800000 820000 161 >, + < 729600000 830000 181 >, + < 806400000 840000 202 >, + < 883200000 850000 223 >, + < 960000000 860000 245 >; + + qcom,speed2-pvs2-bin-v0 = + < 300000000 775000 72 >, + < 345600000 775000 83 >, + < 422400000 775000 102 >, + < 499200000 785000 121 >, + < 576000000 795000 141 >, + < 652800000 805000 161 >, + < 729600000 815000 181 >, + < 806400000 825000 202 >, + < 883200000 835000 223 >, + < 960000000 845000 245 >; + + qcom,speed2-pvs3-bin-v0 = + < 300000000 775000 72 >, + < 345600000 775000 83 >, + < 422400000 775000 102 >, + < 499200000 775000 121 >, + < 576000000 780000 141 >, + < 652800000 790000 161 >, + < 729600000 800000 181 >, + < 806400000 810000 202 >, + < 883200000 820000 223 >, + < 960000000 830000 245 >; + + qcom,speed2-pvs4-bin-v0 = + < 300000000 775000 72 >, + < 345600000 775000 83 >, + < 422400000 775000 102 >, + < 499200000 775000 121 >, + < 576000000 775000 141 >, + < 652800000 780000 161 >, + < 729600000 790000 181 >, + < 806400000 800000 202 >, + < 883200000 810000 223 >, + < 960000000 820000 245 >; + + qcom,speed2-pvs5-bin-v0 = + < 300000000 750000 72 >, + < 345600000 750000 83 >, + < 422400000 750000 102 >, + < 499200000 750000 121 >, + < 576000000 760000 141 >, + < 652800000 770000 161 >, + < 729600000 780000 181 >, + < 806400000 790000 202 >, + < 883200000 800000 223 >, + < 960000000 810000 245 >; + + qcom,speed2-pvs6-bin-v0 = + < 300000000 750000 72 >, + < 345600000 750000 83 >, + < 422400000 750000 102 >, + < 499200000 750000 121 >, + < 576000000 750000 141 >, + < 652800000 760000 161 >, + < 729600000 770000 181 >, + < 806400000 780000 202 >, + < 883200000 790000 223 >, + < 960000000 800000 245 >; + + qcom,speed1-pvs0-bin-v0 = + < 300000000 775000 72 >, + < 345600000 775000 83 >, + < 422400000 775000 101 >, + < 499200000 780000 120 >, + < 576000000 790000 139 >, + < 652800000 800000 159 >, + < 729600000 810000 180 >, + < 806400000 820000 200 >, + < 883200000 830000 221 >, + < 960000000 840000 242 >; + + qcom,speed1-pvs1-bin-v0 = + < 300000000 775000 72 >, + < 345600000 775000 83 >, + < 422400000 775000 101 >, + < 499200000 775000 120 >, + < 576000000 775000 139 >, + < 652800000 785000 159 >, + < 729600000 795000 180 >, + < 806400000 805000 200 >, + < 883200000 815000 221 >, + < 960000000 825000 242 >; + + qcom,speed1-pvs2-bin-v0 = + < 300000000 750000 72 >, + < 345600000 750000 83 >, + < 422400000 750000 101 >, + < 499200000 750000 120 >, + < 576000000 760000 139 >, + < 652800000 770000 159 >, + < 729600000 780000 180 >, + < 806400000 790000 200 >, + < 883200000 800000 221 >, + < 960000000 810000 242 >; + + qcom,speed1-pvs3-bin-v0 = + < 300000000 750000 72 >, + < 345600000 750000 83 >, + < 422400000 750000 101 >, + < 499200000 750000 120 >, + < 576000000 750000 139 >, + < 652800000 755000 159 >, + < 729600000 765000 180 >, + < 806400000 775000 200 >, + < 883200000 785000 221 >, + < 960000000 795000 242 >; + + qcom,speed1-pvs4-bin-v0 = + < 300000000 750000 72 >, + < 345600000 750000 83 >, + < 422400000 750000 101 >, + < 499200000 750000 120 >, + < 576000000 750000 139 >, + < 652800000 750000 159 >, + < 729600000 755000 180 >, + < 806400000 765000 200 >, + < 883200000 775000 221 >, + < 960000000 785000 242 >; + + qcom,speed1-pvs5-bin-v0 = + < 300000000 725000 72 >, + < 345600000 725000 83 >, + < 422400000 725000 101 >, + < 499200000 725000 120 >, + < 576000000 725000 139 >, + < 652800000 735000 159 >, + < 729600000 745000 180 >, + < 806400000 755000 200 >, + < 883200000 765000 221 >, + < 960000000 775000 242 >; + + qcom,speed1-pvs6-bin-v0 = + < 300000000 725000 72 >, + < 345600000 725000 83 >, + < 422400000 725000 101 >, + < 499200000 725000 120 >, + < 576000000 725000 139 >, + < 652800000 725000 159 >, + < 729600000 735000 180 >, + < 806400000 745000 200 >, + < 883200000 755000 221 >, + < 960000000 765000 242 >; + }; + + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v2"; + #clock-cells = <1>; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -144,6 +417,36 @@ }; }; + clock-controller@f9016000 { + compatible = "qcom,hfpll"; + reg = <0xf9016000 0x30>; + clock-output-names = "hfpll_l2"; + }; + + clock-controller@f908a000 { + compatible = "qcom,hfpll"; + reg = <0xf908a000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll0"; + }; + + clock-controller@f909a000 { + compatible = "qcom,hfpll"; + reg = <0xf909a000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll1"; + }; + + clock-controller@f90aa000 { + compatible = "qcom,hfpll"; + reg = <0xf90aa000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll2"; + }; + + clock-controller@f90ba000 { + compatible = "qcom,hfpll"; + reg = <0xf90ba000 0x30>, <0xf900a000 0x30>; + clock-output-names = "hfpll3"; + }; + saw_l2: regulator@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; -- cgit v1.2.3 From 9d9ec6d06dd76bdcc350c77d702c5d931b0efc80 Mon Sep 17 00:00:00 2001 From: Pramod Gurav Date: Tue, 21 Oct 2014 11:23:19 +0530 Subject: ARM: DT: apq8064: Add Support for SD Card Detect for ifc6410 board This changes muxes in gpio26 pin to function as gpio and adds support for sd card detect for apq8064 based IFC6410 board. Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala Cc: Russell King Cc: Srinivas Kandagatla Signed-off-by: Pramod Gurav --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index dbb33cb3df82..b06ff90c8eef 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -13,6 +13,14 @@ function = "gsbi1"; }; }; + + card_detect: card_detect { + mux { + pins = "gpio26"; + function = "gpio"; + bias-disable; + }; + }; }; gsbi@12440000 { @@ -103,6 +111,9 @@ /* External micro SD card */ sdcc3: sdcc@12180000 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; }; /* WLAN */ sdcc4: sdcc@121c0000 { -- cgit v1.2.3 From dec9df6d347ef380e8bb8f194b8bf1674ce1008d Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Fri, 24 Oct 2014 17:40:18 -0600 Subject: arm: dts: qcom: Add power-controller device node for 8974 Krait CPUs Each Krait CPU in the QCOM 8974 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core. Signed-off-by: Lina Iyer --- arch/arm/boot/dts/qcom-msm8974.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 45ff96d74079..a200883f7fed 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -24,6 +24,7 @@ clocks = <&kraitcc 0>; clock-names = "cpu"; clock-latency = <100000>; + qcom,saw = <&saw0>; }; cpu1: cpu@1 { @@ -36,6 +37,7 @@ clocks = <&kraitcc 1>; clock-names = "cpu"; clock-latency = <100000>; + qcom,saw = <&saw1>; }; cpu2: cpu@2 { @@ -48,6 +50,7 @@ clocks = <&kraitcc 2>; clock-names = "cpu"; clock-latency = <100000>; + qcom,saw = <&saw2>; }; cpu3: cpu@3 { @@ -60,6 +63,7 @@ clocks = <&kraitcc 3>; clock-names = "cpu"; clock-latency = <100000>; + qcom,saw = <&saw3>; }; L2: l2-cache { @@ -447,7 +451,27 @@ clock-output-names = "hfpll3"; }; - saw_l2: regulator@f9012000 { + saw0: power-controller@f9089000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf9089000 0x1000>; + }; + + saw1: power-controller@f9099000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf9099000 0x1000>; + }; + + saw2: power-controller@f90a9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf90a9000 0x1000>; + }; + + saw3: power-controller@f90b9000 { + compatible = "qcom,msm8974-saw2-v2.1-cpu"; + reg = <0xf90b9000 0x1000>; + }; + + saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator; -- cgit v1.2.3 From 41ef4aa45a609262398341461918115b4d6bfbdb Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Fri, 24 Oct 2014 17:40:19 -0600 Subject: arm: dts: qcom: Add power-controller device node for 8084 Krait CPUs Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core. Signed-off-by: Lina Iyer --- arch/arm/boot/dts/qcom-apq8084.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 1f130bc16858..4466b9e1e121 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -21,6 +21,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc0>; + qcom,saw = <&saw0>; }; cpu@1 { @@ -30,6 +31,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc1>; + qcom,saw = <&saw1>; }; cpu@2 { @@ -39,6 +41,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc2>; + qcom,saw = <&saw2>; }; cpu@3 { @@ -48,6 +51,7 @@ enable-method = "qcom,kpss-acc-v2"; next-level-cache = <&L2>; qcom,acc = <&acc3>; + qcom,saw = <&saw3>; }; L2: l2-cache { @@ -144,7 +148,27 @@ }; }; - saw_l2: regulator@f9012000 { + saw0: power-controller@f9089000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu"; + reg = <0xf9089000 0x1000>; + }; + + saw1: power-controller@f9099000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu"; + reg = <0xf9099000 0x1000>; + }; + + saw2: power-controller@f90a9000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu"; + reg = <0xf90a9000 0x1000>; + }; + + saw3: power-controller@f90b9000 { + compatible = "qcom,apq8084-saw2-v2.1-cpu"; + reg = <0xf90b9000 0x1000>; + }; + + saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; regulator; -- cgit v1.2.3 From 2f96b75d07bbf8bbbdaffd4afcb79879833d4dee Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Fri, 24 Oct 2014 17:40:20 -0600 Subject: arm: dts: qcom: Update power-controller device node for 8064 Krait CPUs Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible binding string to configure SPM registers and allow the SPM to put the core in deeper idle states when the core is idle. Signed-off-by: Lina Iyer --- arch/arm/boot/dts/qcom-apq8064.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 158fdb4fb694..f8d44863f87d 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -386,26 +386,26 @@ clock-output-names = "acpu_l2_aux"; }; - saw0: regulator@2089000 { - compatible = "qcom,saw2"; + saw0: power-controller@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: regulator@2099000 { - compatible = "qcom,saw2"; + saw1: power-controller@2099000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw2: regulator@20a9000 { - compatible = "qcom,saw2"; + saw2: power-controller@20a9000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw3: regulator@20b9000 { - compatible = "qcom,saw2"; + saw3: power-controller@20b9000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; }; -- cgit v1.2.3 From 834ff133202b02c6a45ea450c7e205dc68e4b803 Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Fri, 24 Oct 2014 17:40:22 -0600 Subject: arm: dts: qcom: Add idle states device nodes for 8974 Add allowable C-States for each cpu using the cpu-idle-states node. Support Standby and Standalone power collapse (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: Lina Iyer --- arch/arm/boot/dts/qcom-msm8974.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index a200883f7fed..819a6f407e70 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -25,6 +25,7 @@ clock-names = "cpu"; clock-latency = <100000>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu1: cpu@1 { @@ -38,6 +39,7 @@ clock-names = "cpu"; clock-latency = <100000>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ clock-names = "cpu"; clock-latency = <100000>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu3: cpu@3 { @@ -64,6 +67,7 @@ clock-names = "cpu"; clock-latency = <100000>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; L2: l2-cache { @@ -71,6 +75,22 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_STBY: standby { + compatible = "qcom,idle-state-stby", "arm,idle-state"; + entry-latency-us = <1>; + exit-latency-us = <1>; + min-residency-us = <2>; + }; + + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu { -- cgit v1.2.3 From b332d65491742e540dea4bb5b46a580abd3d25ed Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Fri, 24 Oct 2014 17:40:23 -0600 Subject: arm: dts: qcom: Add idle states device nodes for 8084 Add allowable C-States for each cpu using the cpu-idle-states node. Support standby and standalone power collapse (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: Lina Iyer --- arch/arm/boot/dts/qcom-apq8084.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 4466b9e1e121..207be157b9a7 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -22,6 +22,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu@1 { @@ -32,6 +33,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu@2 { @@ -42,6 +44,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu@3 { @@ -52,6 +55,7 @@ next-level-cache = <&L2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; L2: l2-cache { @@ -59,6 +63,22 @@ cache-level = <2>; qcom,saw = <&saw_l2>; }; + + idle-states { + CPU_STBY: standby { + compatible = "qcom,idle-state-stby", "arm,idle-state"; + entry-latency-us = <1>; + exit-latency-us = <1>; + min-residency-us = <2>; + }; + + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <150>; + exit-latency-us = <200>; + min-residency-us = <2000>; + }; + }; }; cpu-pmu { -- cgit v1.2.3 From 6c7275d4ac10fe5a6452039d6d10024c07f4329e Mon Sep 17 00:00:00 2001 From: Lina Iyer Date: Fri, 24 Oct 2014 17:40:24 -0600 Subject: arm: dts: qcom: Add idle state device nodes for 8064 Add ARM common idle state device bindings for cpuidle support in APQ8064. Signed-off-by: Lina Iyer --- arch/arm/boot/dts/qcom-apq8064.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch') diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index f8d44863f87d..d5799d841c69 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -29,6 +29,7 @@ clocks = <&kraitcc 0>; clock-names = "cpu"; clock-latency = <100000>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu@1 { @@ -42,6 +43,7 @@ clocks = <&kraitcc 1>; clock-names = "cpu"; clock-latency = <100000>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu@2 { @@ -55,6 +57,7 @@ clocks = <&kraitcc 2>; clock-names = "cpu"; clock-latency = <100000>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; cpu@3 { @@ -68,12 +71,30 @@ clocks = <&kraitcc 3>; clock-names = "cpu"; clock-latency = <100000>; + cpu-idle-states = <&CPU_STBY &CPU_SPC>; }; L2: l2-cache { compatible = "cache"; cache-level = <2>; }; + + idle-states { + CPU_STBY: standby { + compatible = "qcom,idle-state-stby", "arm,idle-state"; + entry-latency-us = <1>; + exit-latency-us = <1>; + min-residency-us = <2>; + }; + + CPU_SPC: spc { + compatible = "qcom,idle-state-spc", "arm,idle-state"; + entry-latency-us = <400>; + exit-latency-us = <900>; + min-residency-us = <3000>; + }; + }; + }; cpu-pmu { -- cgit v1.2.3