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* tracking-qcomlt-dt:
arm: dts: qcom: Add idle state device nodes for 8064
arm: dts: qcom: Add idle states device nodes for 8084
arm: dts: qcom: Add idle states device nodes for 8974
arm: dts: qcom: Update power-controller device node for 8064 Krait CPUs
arm: dts: qcom: Add power-controller device node for 8084 Krait CPUs
arm: dts: qcom: Add power-controller device node for 8974 Krait CPUs
ARM: DT: apq8064: Add Support for SD Card Detect for ifc6410 board
ARM: dts: qcom: Add necessary DT data for Krait cpufreq
WIP: ARM: DT: ifc6410 : add lvds panel
WIP: ARM: DT: APQ8064: Add iommu
ARM: DT: APQ8064: Add MDP support
ARM: DT: ifc6410: add wlan node with reset line.
ARM: DT: apq8064: Add pmic gpio node
ARM: DT: apq8064: add pci support
ARM: DT: apq8064: Add SATA controller support.
ARM: DT: apq8064: Add USB OTG support
ARM: DT: apq8064: Add usb host support.
ARM: DT: apq8064: add rpm support
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* tracking-qcomlt-cpuidle:
qcom: scm: fix compliation error.
qcom: cpuidle: Add cpuidle driver for QCOM cpus
qcom: spm: Add Subsystem Power Manager driver
qcom: scm: scm_set_warm_boot_addr() to set the warmboot address
ARM: qcom: Move scm-boot files to drivers/soc and include/soc
ARM: qcom: Add SCM warmboot flags for quad core targets.
ARM: qcom: scm: Add atomic SCM APIs
ARM: qcom: scm: Move the scm driver to drivers/soc/qcom
ARM: qcom: scm: Add logging of actual return code from scm call
ARM: qcom: scm: Flush the command buffer only instead of the entire cache
ARM: qcom: scm: Get cacheline size from CTR
ARM: qcom: scm: Fix incorrect cache invalidation
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* tracking-qcomlt-cpufreq:
cpufreq:qcom: covert to use cpufreq-dt
cpufreq: Add module to register cpufreq on Krait CPUs
clk: qcom: Add Krait clock controller driver
clk: qcom: Add KPSS ACC/GCC driver
clk: qcom: Add support for Krait clocks
clk: qcom: Add IPQ806X's HFPLLs
clk: qcom: Add MSM8960/APQ8064's HFPLLs
clk: qcom: Add HFPLL driver
clk: qcom: Add support for High-Frequency PLLs (HFPLLs)
clk: Avoid sending high rates to downstream clocks during set_rate
clk: Add safe switch hook
clk: divider: Make generic for usage elsewhere
ARM: Add Krait L2 register accessor functions
clk: Add __clk_mux_determine_rate_closest
clk: mux: Split out register accessors for reuse
clk: mux: Add unregistration API
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* tracking-qcomlt-pcie:
pci: qcom: move device init to subsys_initcall_sync
pci: qcom: add msi support
pci: qcom: Add support to external phy reference clk.
pci: qcom: remove static declaration of functions.
pci: qcom: Add regulator support
pci: qcom: move dt parsing code out of probe
pci: qcom: fix unused variable warning.
pci: qcom: fix a typo in reset gpio
PCI: qcom: Add support for pcie controllers on IPQ8064
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* tracking-qcomlt-fixes:
defconfig: qcom: add qcom specific configs.
clk: qcom: Fix duplicate rbcpr clock name
arm: vfp: Bounce undefined instructions in vectored mode
ARM: vfp: Fix VFPv3 hwcap detection on CPUID based cpus
ARM: vfp: Workaround bad MVFR1 register on some Kraits
iommu:msm: fix compilation error.
fixup: ATAG MEM fixup loader for Qualcomm devices
ARM: multi_v7_defconfig: Add QCOM specific drivers
mfd: ssbi: promote the driver to subsys level
arm: Fix DEBUG_LL for multi-platform kernels (without PL01X)
arm: Seperate DEBUG_UART_PHYS from DEBUG_LL on EP93XX
arm: sa1100: Migrate DEBUG_LL macros to shared directory
arm: netx: Migrate DEBUG_LL macros to shared directory
arm: omap1: Migrate debug_ll macros to use 8250.S
arm: ks8695: Migrate debug_ll macros to shared directory
arm: Remove DEBUG_LL_UART_NONE
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Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Add ARM common idle state device bindings for cpuidle support in
APQ8064.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Add allowable C-States for each cpu using the cpu-idle-states node.
Support standby and standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Add allowable C-States for each cpu using the cpu-idle-states node.
Support Standby and Standalone power collapse (power down that does not
affect any SoC idle states) for each cpu.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible
binding string to configure SPM registers and allow the SPM to put the
core in deeper idle states when the core is idle.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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Each Krait CPU in the QCOM 8974 SoC has an SAW power controller to
regulate the power to the cpu and aide the core in entering idle states.
Reference the SAW instance and associate the instance with the CPU core.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
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This changes muxes in gpio26 pin to function as gpio and adds support
for sd card detect for apq8064 based IFC6410 board.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com>
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Add the necessary DT nodes and data so we can probe the cpufreq
driver on MSM devices with Krait CPUs.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds MDP node to APQ8064 dt.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds wlan node with platform specfic reset gpio line.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds pmic gpio node to the device tree, this node is
necessary for devices like wlan to control reset gpio.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds PCIE support to APQ8064, tested on IFC6410 board.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds AHCI based SATA controller support to APQ8064.
Tested on IFC6410 board.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds USB OTG support on USB1 of APQ8064 SOC.
Tested on IFC6410 with ethernet gadget.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds device tree nodes to support two usb hosts on APQ8064
SOC.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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This patch adds rpm node to apq8064 dt as rpm would be used by other
devices for regulator support.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Follow the scm.c and move scm-boot files to drivers/soc/qcom. The
guidance is to clean files out from mach-qcom and move to drivers/soc
area.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Quad core targets like APQ8074, APQ8064, APQ8084 need SCM support set up
warm boot addresses in the Secure Monitor. Extend the SCM flags to
support warmboot addresses for secondary cores.
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Architectural changes in the ARM Linux kernel tree mandate the eventual
removal of the mach-* directories. Move the scm driver to
drivers/soc/qcom and the scm header to include/soc/qcom to support that
removal.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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When an error occurs during an scm call the error returned is remapped so
we lose the original error code. This means that when an error occurs we
have no idea what actually failed within the secure environment.
Add a logging statement that will log the actual error code from scm call
allowing us to easily determine what caused the error to occur.
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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scm_call flushes the entire cache before calling into the secure world.
This is both a performance penalty as well as insufficient on SMP systems
where the CPUs possess a write-back L1 cache. Flush only the command and
response buffers instead, moving the responsibility of flushing any other
cached buffer (being passed to the secure world) to callers.
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Instead of hardcoding the cacheline size as 32, get the cacheline size from
the CTR register.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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The cache invalidation in scm_call() correctly rounds down the start
address to invalidate the beginning of the cacheline but doesn't properly
round up the 'end' address to make it aligned. The last chunk of the
buffer won't be invalidated when 'end' is not cacheline size aligned so
make sure to invalidate the last few bytes in such situations. It also
doesn't do anything about outer caches so make sure to invalidate and flush
those as well.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
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Krait CPUs have a handful of L2 cache controller registers that
live behind a cp15 based indirection register. First you program
the indirection register (l2cpselr) to point the L2 'window'
register (l2cpdr) at what you want to read/write. Then you
read/write the 'window' register to do what you want. The
l2cpselr register is not banked per-cpu so we must lock around
accesses to it to prevent other CPUs from re-pointing l2cpdr
underneath us.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Courtney Cavin <courtney.cavin@sonymobile.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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fixed checkpatch warnings too.
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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Certain ARM CPU implementations (e.g. Cortex-A15) may not raise a
floating- point exception whenever deprecated short-vector VFP
instructions are executed. Instead these instructions are treated
as UNALLOCATED. Change the VFP exception handling code to emulate
short-vector instructions even if FPEXC exception bits are not
set.
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Tested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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The subarchitecture field in the fpsid register is 7 bits wide on
ARM CPUs using the CPUID identification scheme, spanning bits 22
to 16. The topmost bit is used to designate that the
subarchitecture designer is not ARM when it is set to 1. On
non-CPUID scheme CPUs the subarchitecture field is only 4 bits
wide and the higher bits are used to indicate no double precision
support (bit 20) and the FTSMX/FLDMX format (bits 21-22).
The VFP support code only looks at bits 19-16 to determine the
VFP version. On Qualcomm's processors (Krait and Scorpion) we
should see that we have HWCAP_VFPv3 but we don't because bit 22
is set to 1 to indicate that the subarchitecture is not
implemented by ARM and the rest of the bits are left as 0 because
this is the first subarchitecture that Qualcomm has designed.
Unfortunately we can't just widen the FPSID subarchitecture
bitmask to consider all the bits on a CPUID scheme because there
may be CPUs without the CPUID scheme that have VFP without double
precision support and then the version would be a very wrong and
large number. Instead, update the version detection logic to
consider if the CPU is using the CPUID scheme.
If the CPU is using CPUID scheme, use the MVFR registers to
determine what version of VFP is supported. We already do this
for VFPv4, so do something similar for VFPv3 and look for single
or double precision support in MVFR0. Otherwise fall back to
using FPSID to detect VFP suppport on non-CPUID scheme CPUs. We
know that VFPv3 is only present in CPUs that have support for the
CPUID scheme so this should be equivalent.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Certain versions of the Krait processor don't report that they
support the fused multiply accumulate instruction via the MVFR1
register despite the fact that they actually do. Unfortunately we
use this register to identify support for VFPv4. Override the
hwcap on all Krait processors to indicate support for VFPv4 to
workaround this.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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This patch adds common kconfig options required for qcom chips to work.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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When building a multi_v7_defconfig kernel it is not possible to configure
DEBUG_LL to use any serial device except a ARM Primecell PL01X, or more
accurately and worse, it is possible to configure a different serial
device but KConfig does not honour this request. In fact this also
overrides the user selection for some of the single platform kernels, for
example I don't think DEBUG_LL can be targetted at ICE or semihosted
supervisor for ARCH_VERSATILE.
This happens because DEBUG_UART_PL01X is automatically enabled by
some architectures and this means user decisions made regarding
the DEBUG_LL backend will be overriden. Problem is fixed by removing the
automatic enabling of this option.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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On EP93XX uncompress.h uses CONFIG_DEBUG_UART_PHYS instead of a hard
coded serial port. This means the build breaks when DEBUG_LL
(and DEBUG_LL_UART_PL01X) is not enabled.
This is fixed by adding a new dependancy.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
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As part of the migration we copy a few definitions from the mach-sa1100
headers and replace the automatic serial port detectiion with explicit
configuration based on DEBUG_UART_PHYS/DEBUG_UART_VIRT.
The removal of the automatic configuration is similar to the way migration
was handled for OMAP2 (see 808b7e07464d...).
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
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As part of the migration we introduce DEBUG_UART_PHYS/DEBUG_UART_VIRT
which default to UART1 but allow a user to configure UART2 or UART3.
We also introduce symbolic names for the registers and flags.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Acked-by: Arnd Bergmann <arnd.bergmann@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org
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The omap1's debug-macro.S is similar to the generic 8250 code. Compared to
the 8520 code the omap1 macro automatically determines what UART to use
based on breadcrumbs left by the bootloader and automatically copes with
the eccentric register layout on OMAP7XX.
This patch drops both these features and relies instead on the generic
8250 macros:
1. Dropping support for the bootloader breadcrumbs is identical to the
way the migration was handled for OMAP2 (see 808b7e07464d...).
2. Support for OMAP7XX still exists but it must be configured by hand
(DEBUG_OMAP7XXUART1/2/3) rather than handled at runtime.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Tony Lindgren <tony@atomide.com>
Cc: Arnd Bergmann <arnd.bergmann@linaro.org>
Cc: linux-omap@vger.kernel.org
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
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As part of the migration a couple of uart definitions have been copied
from of the platform specific header files.
Note that, in order to keep oldconfig working nicely we must defer the
removal of arch/arm/mach-ks8695/include/mach/debug-macro.S until
DEBUG_LL_UART_NONE has been removed.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Greg Ungerer <gerg@uclinux.org>
Cc: Arnd Bergmann <arnd.bergmann@linaro.org>
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Only a very small handful of platforms support DEBUG_LL_UART_NONE but it
lurks in the menus of every single platform config ready to break the
build. This is an especial problem for defconfig/oldconfig since it is
often selected by default.
This patch solves the problem by removing this option. Any platforms
still depending upon this option must be migrated.
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Russell King <linux@arm.linux.org.uk>
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This patch adds wlan reset functionality to board specific data as sdio
device does not support platform speific data from DT yet.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux
Pull arm64 fixes from Catalin Marinas:
- enable bpf syscall for compat
- cpu_suspend fix when checking the idle state type
- defconfig update
* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
arm64: defconfig: update defconfig for 3.18
arm64: compat: Enable bpf syscall
arm64: psci: fix cpu_suspend to check idle state type for index
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Another quiet week:
- a fix to silence edma probe error on non-supported platforms from
Arnd
- a fix to enable the PL clock for Parallella, to make mainline
usable with the SDK.
- a somewhat verbose fix for the PLL clock tree on VF610
- enabling of SD/MMC on one of the VF610-based boards (for testing)
- a fix for i.MX where CONFIG_SPI used to be implicitly enabled and
now needs to be added to the defconfig instead
- another maintainer added for bcm2835: Lee Jones"
* tag 'armsoc-for-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: dts: zynq: Enable PL clocks for Parallella
dma: edma: move device registration to platform code
ARM: dts: vf610: add SD node to cosmic dts
MAINTAINERS: update bcm2835 entry
ARM: imx: Fix the removal of CONFIG_SPI option
ARM: imx: clk-vf610: define PLL's clock tree
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The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.
Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.
Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.
Cc: <stable@vger.kernel.org> # 3.17.x
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Pull MIPS updates from Ralf Baechle:
"This weeks' round of MIPS bug fixes for 3.18:
- wire up the bpf syscall
- fix TLB dump output for R3000 class TLBs
- fix strnlen_user return value if no NUL character was found.
- fix build with binutils 2.24.51+. While there is no binutils 2.25
release yet, toolchains derived from binutils 2.24.51+ are already
in common use.
- the Octeon GPIO code forgot to offline GPIO IRQs.
- fix build error for XLP.
- fix possible BUG assertion with EVA for CMA"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: Fix build with binutils 2.24.51+
MIPS: R3000: Fix debug output for Virtual page number
MIPS: Fix strnlen_user() return value in case of overlong strings.
MIPS: CMA: Do not reserve memory if not required
MIPS: Wire up bpf syscall.
MIPS/Xlp: Remove the dead function destroy_irq() to fix build error
MIPS: Octeon: Make Octeon GPIO IRQ chip CPU hotplug-aware
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Starting with version 2.24.51.20140728 MIPS binutils complain loudly
about mixing soft-float and hard-float object files, leading to this
build failure since GCC is invoked with "-msoft-float" on MIPS:
{standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
LD arch/mips/alchemy/common/built-in.o
mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
arch/mips/alchemy/common/sleeper.o uses -mhard-float
To fix this, we detect if GAS is new enough to support "-msoft-float" command
option, and if it does, we can let GCC pass it to GAS; but then we also need
to sprinkle the files which make use of floating point registers with the
necessary ".set hardfloat" directives.
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: Markos Chandras <Markos.Chandras@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8355/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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