From 23ccf530431561268b0190f0f1b740b618771b7b Mon Sep 17 00:00:00 2001 From: Andrew Cooper Date: Fri, 2 Apr 2021 14:10:25 +0100 Subject: x86/cpuid: Advertise no-lmsl unilaterally to hvm guests While part of the original AMD64 spec, Long Mode Segment Limit was a feature not picked up by Intel, and therefore didn't see much adoption in software. AMD have finally dropped the feature from hardware, and allocated a CPUID bit to indicate its absence. Xen has never supported the feature for guests, even when running on capable hardware, so advertise the feature's absence unilaterally. There is nothing specifically wrong with exposing this bit to PV guests, but the PV ABI doesn't include a working concept of MSR_EFER in the first place, so exposing it to PV guests would be out-of-place. Signed-off-by: Andrew Cooper Reviewed-by: Jan Beulich --- xen/include/public/arch-x86/cpufeatureset.h | 1 + 1 file changed, 1 insertion(+) (limited to 'xen/include/public') diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index a501479820..42bc8d4279 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -255,6 +255,7 @@ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error pointers */ XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */ XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */ +XEN_CPUFEATURE(NO_LMSL, 8*32+20) /*S EFER.LMSLE no longer supported. */ XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number */ /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ -- cgit v1.2.3