summaryrefslogtreecommitdiff
path: root/xen/include/asm-x86/msr-index.h
AgeCommit message (Expand)Author
2022-02-08x86/tsx: Cope with TSX deprecation on WHL-R/CFL-RAndrew Cooper
2021-10-20x86/hpet: Use another crystalball to evaluate HPET usabilityThomas Gleixner
2021-09-08x86/msr: Cleanup of misc constantsAndrew Cooper
2021-09-08x86/msr: Clean up the MSR_EFER constantsAndrew Cooper
2021-09-08x86/amd: Enumeration for speculative features/hintsAndrew Cooper
2021-07-09x86/AMD: drop MSR_K7_HWCRJan Beulich
2021-07-09x86/AMD: expose SYSCFG, TOM, TOM2, and IORRs to Dom0Jan Beulich
2021-06-09x86/tsx: Cope with TSX deprecation on SKL/KBL/CFL/WHLAndrew Cooper
2021-04-26x86/vtx: add LBR_SELECT to the list of LBR MSRsIgor Druzhinin
2021-03-12x86/AMD: expose HWCR.TscFreqSel to guestsJan Beulich
2021-01-29x86: Support booting under Secure Startup via SKINITNorbert Kamiński
2020-12-31x86/svm: Clean up MSR_K8_VM_CR definitionsAndrew Cooper
2020-09-21x86/svm: ignore accesses to EX_CFGRoger Pau Monné
2020-07-20x86/vmx: add Intel PT MSR definitionsMichal Leszczynski
2020-06-26x86/msr: Disallow access to Processor Trace MSRsAndrew Cooper
2020-06-09x86/spec-ctrl: CPUID/MSR definitions for Special Register Buffer Data SamplingAndrew Cooper
2020-05-29x86/S3: Save and restore Shadow Stack configurationAndrew Cooper
2020-05-29x86emul: support ENQCMD insnsJan Beulich
2020-04-21x86: Enumeration for Control-flow Enforcement TechnologyAndrew Cooper
2020-02-21x86/msr: Start cleaning up msr-index.hAndrew Cooper
2020-02-21x86/splitlock: CPUID and MSR detailsAndrew Cooper
2019-12-18x86: include the PPIN in MCE records when availableJan Beulich
2019-11-12x86/spec-ctrl: Mitigate the TSX Asynchronous Abort sidechannelAndrew Cooper
2019-11-12x86/tsx: Introduce tsx= to use MSR_TSX_CTRL when availableAndrew Cooper
2019-11-12x86/vtx: Disable executable EPT superpages to work around CVE-2018-12207Andrew Cooper
2019-05-14x86/spec-ctrl: CPUID/MSR definitions for Microarchitectural Data SamplingAndrew Cooper
2019-05-13x86/msr: Definitions for MSR_INTEL_CORE_THREAD_COUNTAndrew Cooper
2019-03-18x86/msr: Shorten ARCH_CAPABILITIES_* constantsAndrew Cooper
2019-03-12x86/tsx: Implement controls for RTM force-abort modeAndrew Cooper
2018-12-05x86: Fix APIC MSR constant namesAndrew Cooper
2018-08-14x86/spec-ctrl: CPUID/MSR definitions for L1D_FLUSHAndrew Cooper
2018-07-24x86/svm: Drop the suggestion of Long Mode Segment Limit supportAndrew Cooper
2018-07-16x86/mtrr: split "enabled" field into two boolean flagsJan Beulich
2018-07-05x86/mtrr: introduce mask to get VCNT from MTRRcap MSRRoger Pau Monné
2018-05-22x86/spec-ctrl: Rename ARCH_CAPS.SSBD_NO to SSB_NOAndrew Cooper
2018-05-21x86/Intel: Mitigations for GPZ SP4 - Speculative Store BypassAndrew Cooper
2018-05-07x86/pv: Hide more EFER bits from PV guestsAndrew Cooper
2018-04-19x86/spec_ctrl: Updates to retpoline-safety decision makingAndrew Cooper
2018-04-05x86: disable XPTI when RDCL_NOJan Beulich
2018-01-26x86/msr: Emulation of MSR_{SPEC_CTRL,PRED_CMD} for guestsAndrew Cooper
2018-01-16x86/feature: Definitions for Indirect Branch ControlsAndrew Cooper
2018-01-16x86/amd: Try to set lfence as being Dispatch SerialisingAndrew Cooper
2017-12-15x86: implement data structure and CPU init flow for MBAYi Sun
2017-10-03x86/msr: Correct the definition of MSR_IA32_APICBASE_BASEAndrew Cooper
2017-08-03x86: L2 CAT: implement CPU init flow.Yi Sun
2017-07-04x86/mce_intel: detect and enable LMCE on Intel hostHaozhong Zhang
2017-02-27x86/vmx: fix vmentry failure with TSX bits in LBRSergey Dyasli
2016-09-26x86/AMD: apply erratum 665 workaroundEmanuel Czirai
2016-09-07VMX: correct feature checks for MPX and XSAVESJan Beulich
2016-08-04x86: support newer Intel CPU modelsJan Beulich
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-11 06:55:37 +0000