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path: root/xen/arch/arm/vgic-v2.c
AgeCommit message (Expand)Author
2021-10-21xen/arm: vgic: Ignore write access to ICPENDR*Hongda Deng
2021-02-25xen/vgic: Implement write to ISPENDR in vGICv{2, 3}Julien Grall
2018-11-15xen/domain: Allocate d->vcpu[] earlier during domain_create()Andrew Cooper
2018-11-09xen/arm: Only include vreg.h when necessaryJulien Grall
2018-11-09xen/arm: initialize targetStefano Stabellini
2018-06-05xen/arm: Ignore write to GICD_ISACTIVERn registers (vgic-v2)Mirela Simonovic
2018-02-02xen/arm: Don't crash domain on bad MMIO emulationJulien Grall
2017-09-15arm/{v,}gic: switch to plain boolWei Liu
2017-06-23xen/arm: Rename vgic_reg* functions definitions and calls to vreg_reg*Bhupinder Thakur
2017-06-15xen/arm: Use the newly introduced MFN <-> MADDR and GFN <-> MADDR helpersJulien Grall
2017-06-14ARM: vGIC: cache virtual LPI priority in struct pending_irqAndre Przywara
2017-06-14ARM: GICv3: introduce separate pending_irq structs for LPIsAndre Przywara
2017-06-14ARM: vGIC: avoid rank lock when reading priorityAndre Przywara
2017-04-06vgic: refuse irq migration when one is already in progressStefano Stabellini
2017-02-16arm: read/write rank->vcpu atomicallyStefano Stabellini
2017-02-16xen/include: Remove explicit xen/config.h includesAndrew Cooper
2016-12-07xen/arm: vgic: Switch vgic_to_sgi return from int to bool and progate up to...Julien Grall
2016-07-26arm/vgic: Change fixed number of mmio handlers to variable numberShanker Donthineni
2016-07-14xen/arm: vgic: Use dynamic memory allocation for vgic_rdist_regionShanker Donthineni
2016-07-13xen: Use the typesafe mfn and gfn in map_mmio_regions...Julien Grall
2016-01-07xen/arm: ignore writes to GICD_ICACTIVER ... GICD_ICACTIVERNStefano Stabellini
2016-01-05xen/arm: vgic: Clarify some comments after 5d495f4Julien Grall
2015-11-25xen/arm: vgic: Re-order the register emulations to match the memory mapJulien Grall
2015-11-25xen/arm: vgic: Properly emulate the full registerJulien Grall
2015-11-25xen/arm: vgic-v2: Implement correctly ICFGR{0, 1} read-onlyJulien Grall
2015-11-25xen/arm: vgic: Introduce helpers to extract/update/clear/set vGIC register ...Julien Grall
2015-11-25xen/arm: vgic: Optimize the way to store the target vCPU in the rankJulien Grall
2015-11-25xen/arm: vgic-v2: Don't ignore a write in ITARGETSR if one field is 0Julien Grall
2015-11-25xen/arm: vgic-v2: Handle correctly byte write in ITARGETSRJulien Grall
2015-11-25xen/arm: vgic-v2: Implement correctly ITARGETSR0 - ITARGETSR7 read-onlyJulien Grall
2015-10-23xen/arm: gic-v2: Automatically detect aliased GIC400Julien Grall
2015-10-08xen/arm: vgic: Introduce a new field to store the rank index and use itJulien Grall
2015-10-08xen/arm: vgic: Optimize the way to store GICD_IPRIORITYR in the rankJulien Grall
2015-10-08xen/arm: io: Support sign-extension for every read accessJulien Grall
2015-10-08xen/arm: io: Extend write/read handler to pass the register in parameterJulien Grall
2015-10-01xen/arm: vgic-v2: Drop cbase from arch_domainJulien Grall
2015-10-01xen/arm: io: Shorten the name of the fields and clean upJulien Grall
2015-10-01xen/arm: io: Extend write/read handler to pass private dataJulien Grall
2015-09-21xen/arm: vgic-v2: Map the GIC virtual CPU interface with the correct sizeJulien Grall
2015-07-03xen/arm: make domain_max_vcpus return value from vgic_opsChen Baozi
2015-07-03xen/arm: Use AFF1 when translating ICC_SGI1R_EL1 to cpumaskChen Baozi
2015-07-03xen/arm: Merge gicv_setup with vgic_domain_initJulien Grall
2015-04-02xen/arm: vgic: Correctly calculate GICD_TYPER.ITLinesNumberJulien Grall
2015-02-20xen/arm: vgic: Drop unecessary include asm/device.hJulien Grall
2015-02-19xen/arm: vgic: Drop iactive, ipend, pendsgi fieldJulien Grall
2015-02-19xen/arm: vgic-v2: GICD_I{S, C}PENDR* are only word-accessibleJulien Grall
2015-02-19xen/arm: vgic-v2: Take the lock when writing into GICD_CTLRJulien Grall
2015-02-19xen/arm: vgic-v2: Correctly handle RAZ/WI registersJulien Grall
2015-02-19xen/arm: vgic-v2: Correctly set GICD_TYPER.CPUNumberJulien Grall
2015-02-18xen/arm: vgic-v2: Don't crash the hypervisor if the SGI target mode is invalidJulien Grall
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