diff options
| -rw-r--r-- | tools/libs/light/libxl_cpuid.c | 1 | ||||
| -rw-r--r-- | tools/misc/xen-cpuid.c | 1 | ||||
| -rw-r--r-- | xen/arch/x86/cpuid.c | 6 | ||||
| -rw-r--r-- | xen/include/public/arch-x86/cpufeatureset.h | 1 | ||||
| -rwxr-xr-x | xen/tools/gen-cpuid.py | 4 |
5 files changed, 12 insertions, 1 deletions
diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c index 289c59c742..aee28b0430 100644 --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -270,6 +270,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str) {"rstr-fp-err-ptrs", 0x80000008, NA, CPUID_REG_EBX, 2, 1}, {"wbnoinvd", 0x80000008, NA, CPUID_REG_EBX, 9, 1}, {"ibpb", 0x80000008, NA, CPUID_REG_EBX, 12, 1}, + {"no-lmsl", 0x80000008, NA, CPUID_REG_EBX, 20, 1}, {"ppin", 0x80000008, NA, CPUID_REG_EBX, 23, 1}, {"nc", 0x80000008, NA, CPUID_REG_ECX, 0, 8}, diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 2d04162d8d..628e8f5aa2 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -152,6 +152,7 @@ static const char *const str_e8b[32] = [12] = "ibpb", + [20] = "no-lmsl", /* [22] */ [23] = "ppin", }; diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c index 18b08d9b87..050cd5713e 100644 --- a/xen/arch/x86/cpuid.c +++ b/xen/arch/x86/cpuid.c @@ -456,6 +456,12 @@ static void __init calculate_hvm_max_policy(void) __set_bit(X86_FEATURE_X2APIC, hvm_featureset); /* + * We don't support EFER.LMSLE at all. AMD has dropped the feature from + * hardware and allocated a CPUID bit to indicate its absence. + */ + __set_bit(X86_FEATURE_NO_LMSL, hvm_featureset); + + /* * On AMD, PV guests are entirely unable to use SYSENTER as Xen runs in * long mode (and init_amd() has cleared it out of host capabilities), but * HVM guests are able if running in protected mode. diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index a501479820..42bc8d4279 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -255,6 +255,7 @@ XEN_CPUFEATURE(CLZERO, 8*32+ 0) /*A CLZERO instruction */ XEN_CPUFEATURE(RSTR_FP_ERR_PTRS, 8*32+ 2) /*A (F)X{SAVE,RSTOR} always saves/restores FPU Error pointers */ XEN_CPUFEATURE(WBNOINVD, 8*32+ 9) /* WBNOINVD instruction */ XEN_CPUFEATURE(IBPB, 8*32+12) /*A IBPB support only (no IBRS, used by AMD) */ +XEN_CPUFEATURE(NO_LMSL, 8*32+20) /*S EFER.LMSLE no longer supported. */ XEN_CPUFEATURE(AMD_PPIN, 8*32+23) /* Protected Processor Inventory Number */ /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */ diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py index 36f67750e5..b953648b65 100755 --- a/xen/tools/gen-cpuid.py +++ b/xen/tools/gen-cpuid.py @@ -242,7 +242,9 @@ def crunch_numbers(state): # CX16 is only encodable in Long Mode. LAHF_LM indicates that the # SAHF/LAHF instructions are reintroduced in Long Mode. 1GB # superpages, PCID and PKU are only available in 4 level paging. - LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU], + # NO_LMSL indicates the absense of Long Mode Segment Limits, which + # have been dropped in hardware. + LM: [CX16, PCID, LAHF_LM, PAGE1GB, PKU, NO_LMSL], # AMD K6-2+ and K6-III processors shipped with 3DNow+, beyond the # standard 3DNow in the earlier K6 processors. |