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authorJan Beulich <jbeulich@suse.com>2018-11-20 15:05:12 +0100
committerJan Beulich <jbeulich@suse.com>2018-11-20 15:05:12 +0100
commitae9bfa9bc1a05686e68d4d87908312cc76f45c40 (patch)
tree8f446257415eeab4be17dfe6f88b8638cc298647 /xen/include/asm-x86/cpufeature.h
parentcb3b3438c7c73657f3e025f8af8b8dca63fb79d3 (diff)
x86emul: support basic AVX512 moves
Note: SDM Vol 2 rev 067 is not really consistent about EVEX.L'L for LIG insns - the only place where this is made explicit is a table in the section titled "Vector Length Orthogonality": While they tolerate 0, 1, and 2, a value of 3 uniformly leads to #UD. Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
Diffstat (limited to 'xen/include/asm-x86/cpufeature.h')
-rw-r--r--xen/include/asm-x86/cpufeature.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 7e11a458bd..c2b0f6ae4e 100644
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -105,6 +105,7 @@
#define cpu_has_smap boot_cpu_has(X86_FEATURE_SMAP)
#define cpu_has_sha boot_cpu_has(X86_FEATURE_SHA)
#define cpu_has_avx512bw boot_cpu_has(X86_FEATURE_AVX512BW)
+#define cpu_has_avx512vl boot_cpu_has(X86_FEATURE_AVX512VL)
/* CPUID level 0x80000007.edx */
#define cpu_has_itsc boot_cpu_has(X86_FEATURE_ITSC)