diff options
| author | Andrew Cooper <andrew.cooper3@citrix.com> | 2018-09-12 14:36:00 +0100 |
|---|---|---|
| committer | Andrew Cooper <andrew.cooper3@citrix.com> | 2019-03-12 17:05:21 +0000 |
| commit | 6be613f29b4205349275d24367bd4c82fb2960dd (patch) | |
| tree | 1adced3eacb309f1f13912d2d9ab4b319d6c53f4 /xen/include/asm-x86/cpufeature.h | |
| parent | 31e67c156f3f539b6d64f3ace52439c07cb21341 (diff) | |
x86/tsx: Implement controls for RTM force-abort mode
The CPUID bit and MSR are deliberately not exposed to guests, because they
won't exist on newer processors. As vPMU isn't security supported, the
misbehaviour of PCR3 isn't expected to impact production deployments.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Diffstat (limited to 'xen/include/asm-x86/cpufeature.h')
| -rw-r--r-- | xen/include/asm-x86/cpufeature.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h index 1fb9af4b19..745801f3c0 100644 --- a/xen/include/asm-x86/cpufeature.h +++ b/xen/include/asm-x86/cpufeature.h @@ -112,6 +112,9 @@ /* CPUID level 0x80000007.edx */ #define cpu_has_itsc boot_cpu_has(X86_FEATURE_ITSC) +/* CPUID level 0x00000007:0.edx */ +#define cpu_has_tsx_force_abort boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT) + /* Synthesized. */ #define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON) #define cpu_has_cpuid_faulting boot_cpu_has(X86_FEATURE_CPUID_FAULTING) |