diff options
| author | Andrew Cooper <andrew.cooper3@citrix.com> | 2018-04-13 15:42:34 +0000 |
|---|---|---|
| committer | Andrew Cooper <andrew.cooper3@citrix.com> | 2018-05-21 14:20:06 +0100 |
| commit | cd53023df952cf0084be9ee3d15a90f8837049c2 (patch) | |
| tree | 3dda5ed09a6b7f92f9aa91e8a974ead3786f23a7 /xen/arch/x86/msr.c | |
| parent | 9df52a25e0e95a0b9971aa2fc26c5c6a5cbdf4ef (diff) | |
x86/msr: Virtualise MSR_SPEC_CTRL.SSBD for guests to use
Almost all infrastructure is already in place. Update the reserved bits
calculation in guest_wrmsr(), and offer SSBD to guests by default.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Diffstat (limited to 'xen/arch/x86/msr.c')
| -rw-r--r-- | xen/arch/x86/msr.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index da9aa596b1..1e12ccb729 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -197,6 +197,8 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) switch ( msr ) { + uint64_t rsvd; + case MSR_INTEL_PLATFORM_INFO: case MSR_ARCH_CAPABILITIES: /* Read-only */ @@ -232,8 +234,10 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) * Note: SPEC_CTRL_STIBP is specified as safe to use (i.e. ignored) * when STIBP isn't enumerated in hardware. */ + rsvd = ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | + (cp->feat.ssbd ? SPEC_CTRL_SSBD : 0)); - if ( val & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) ) + if ( val & rsvd ) goto gp_fault; /* Rsvd bit set? */ vp->spec_ctrl.raw = val; @@ -252,12 +256,12 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) case MSR_INTEL_MISC_FEATURES_ENABLES: { - uint64_t rsvd = ~0ull; bool old_cpuid_faulting = vp->misc_features_enables.cpuid_faulting; if ( !vp->misc_features_enables.available ) goto gp_fault; + rsvd = ~0ull; if ( dp->plaform_info.cpuid_faulting ) rsvd &= ~MSR_MISC_FEATURES_CPUID_FAULTING; |