diff options
| author | Andrew Cooper <andrew.cooper3@citrix.com> | 2022-01-25 13:39:16 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2022-01-25 13:39:16 +0100 |
| commit | cc6fe1bb13197ddc79af480c3c74ce6d6ed3ef2c (patch) | |
| tree | e5d0d52a12b36933bc881a76a749d02be6afe4ba /xen/arch/x86/msr.c | |
| parent | 20b00921f8a62b1b19d893dd468473161706e02d (diff) | |
x86/msr: Split MSR_SPEC_CTRL handling
In order to fix a VT-x bug, and support MSR_SPEC_CTRL on AMD, move
MSR_SPEC_CTRL handling into the new {pv,hvm}_{get,set}_reg() infrastructure.
Duplicate the msrs->spec_ctrl.raw accesses in the PV and VT-x paths for now.
The SVM path is currently unreachable because of the CPUID policy.
No functional change.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
master commit: 6536688439dbca1d08fd6db5be29c39e3917fb2f
master date: 2022-01-20 16:32:11 +0000
Diffstat (limited to 'xen/arch/x86/msr.c')
| -rw-r--r-- | xen/arch/x86/msr.c | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index b834456c7b..71cbfa8ee3 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -28,6 +28,7 @@ #include <asm/hvm/nestedhvm.h> #include <asm/hvm/viridian.h> #include <asm/msr.h> +#include <asm/pv/domain.h> #include <asm/setup.h> #include <public/hvm/params.h> @@ -265,8 +266,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) case MSR_SPEC_CTRL: if ( !cp->feat.ibrsb ) goto gp_fault; - *val = msrs->spec_ctrl.raw; - break; + goto get_reg; case MSR_INTEL_PLATFORM_INFO: *val = mp->platform_info.raw; @@ -424,6 +424,13 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) return ret; + get_reg: /* Delegate register access to per-vm-type logic. */ + if ( is_pv_domain(d) ) + *val = pv_get_reg(v, msr); + else + *val = hvm_get_reg(v, msr); + return X86EMUL_OKAY; + gp_fault: return X86EMUL_EXCEPTION; } @@ -513,9 +520,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) if ( val & rsvd ) goto gp_fault; /* Rsvd bit set? */ - - msrs->spec_ctrl.raw = val; - break; + goto set_reg; case MSR_PRED_CMD: if ( !cp->feat.ibrsb && !cp->extd.ibpb ) @@ -663,6 +668,13 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) return ret; + set_reg: /* Delegate register access to per-vm-type logic. */ + if ( is_pv_domain(d) ) + pv_set_reg(v, msr, val); + else + hvm_set_reg(v, msr, val); + return X86EMUL_OKAY; + gp_fault: return X86EMUL_EXCEPTION; } |