diff options
| author | Andrew Cooper <andrew.cooper3@citrix.com> | 2018-07-17 13:36:30 +0000 |
|---|---|---|
| committer | Andrew Cooper <andrew.cooper3@citrix.com> | 2019-05-21 10:44:00 +0100 |
| commit | 91f86f8634f99abd8f242943e62452211a09fa0a (patch) | |
| tree | 3987c724101e70cb0fefe407ffb3fc28da8b49f3 /xen/arch/x86/msr.c | |
| parent | 37bb9bb49ad1b21140098b4cf768c60f33309e8b (diff) | |
x86/svm: Drop support for AMD's Lightweight Profiling
Lightweight Profiling was introduced in Bulldozer (Fam15h), but was dropped
from Zen (Fam17h) processors. Furthermore, LWP was dropped from Fam15/16 CPUs
when IBPB for Spectre v2 was introduced in microcode, owing to LWP not being
used in practice.
As a result, CPUs which are operating within specification (i.e. with up to
date microcode) no longer have this feature, and therefore are not using it.
Drop support from Xen. The main motivation here is to remove unnecessary
complexity from CPUID handling, but it also tidies up the SVM code nicely.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Brian Woods <brian.woods@amd.com>
Diffstat (limited to 'xen/arch/x86/msr.c')
| -rw-r--r-- | xen/arch/x86/msr.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 883b57b2d5..5a2ef78849 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -132,6 +132,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) case MSR_FLUSH_CMD: /* Write-only */ case MSR_TSX_FORCE_ABORT: + case MSR_AMD64_LWP_CFG: + case MSR_AMD64_LWP_CBADDR: /* Not offered to guests. */ goto gp_fault; @@ -272,6 +274,8 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) case MSR_ARCH_CAPABILITIES: /* Read-only */ case MSR_TSX_FORCE_ABORT: + case MSR_AMD64_LWP_CFG: + case MSR_AMD64_LWP_CBADDR: /* Not offered to guests. */ goto gp_fault; |