diff options
| author | Andrew Cooper <andrew.cooper3@citrix.com> | 2018-09-12 14:36:00 +0100 |
|---|---|---|
| committer | Andrew Cooper <andrew.cooper3@citrix.com> | 2019-03-12 17:05:21 +0000 |
| commit | 6be613f29b4205349275d24367bd4c82fb2960dd (patch) | |
| tree | 1adced3eacb309f1f13912d2d9ab4b319d6c53f4 /xen/arch/x86/msr.c | |
| parent | 31e67c156f3f539b6d64f3ace52439c07cb21341 (diff) | |
x86/tsx: Implement controls for RTM force-abort mode
The CPUID bit and MSR are deliberately not exposed to guests, because they
won't exist on newer processors. As vPMU isn't security supported, the
misbehaviour of PCR3 isn't expected to impact production deployments.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Diffstat (limited to 'xen/arch/x86/msr.c')
| -rw-r--r-- | xen/arch/x86/msr.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 9bb38b6d66..4df4a59f4d 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -131,6 +131,8 @@ int guest_rdmsr(const struct vcpu *v, uint32_t msr, uint64_t *val) case MSR_PRED_CMD: case MSR_FLUSH_CMD: /* Write-only */ + case MSR_TSX_FORCE_ABORT: + /* Not offered to guests. */ goto gp_fault; case MSR_SPEC_CTRL: @@ -230,6 +232,8 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) case MSR_INTEL_PLATFORM_INFO: case MSR_ARCH_CAPABILITIES: /* Read-only */ + case MSR_TSX_FORCE_ABORT: + /* Not offered to guests. */ goto gp_fault; case MSR_AMD_PATCHLOADER: |