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| author | Andrew Cooper <andrew.cooper3@citrix.com> | 2019-04-30 12:07:04 +0100 |
|---|---|---|
| committer | Andrew Cooper <andrew.cooper3@citrix.com> | 2020-02-20 17:29:50 +0000 |
| commit | 691265f96097d4fe3e46ff4267451d49b30143e6 (patch) | |
| tree | 826f227012108687a63f97a7000bae1e5aaa9e48 /xen/arch/x86/msr.c | |
| parent | 9004d93b68d170f7c3910c46030c095d453bcef5 (diff) | |
x86/msr: Virtualise MSR_PLATFORM_ID properly
This is an Intel-only, read-only MSR related to microcode loading. Expose it
in similar circumstances as the PATCHLEVEL MSR.
This should have been alongside c/s 013896cb8b2 "x86/msr: Fix handling of
MSR_AMD_PATCHLEVEL/MSR_IA32_UCODE_REV"
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Diffstat (limited to 'xen/arch/x86/msr.c')
| -rw-r--r-- | xen/arch/x86/msr.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 785574de67..1cea777680 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -143,6 +143,13 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) /* Not offered to guests. */ goto gp_fault; + case MSR_IA32_PLATFORM_ID: + if ( !(cp->x86_vendor & X86_VENDOR_INTEL) || + !(boot_cpu_data.x86_vendor & X86_VENDOR_INTEL) ) + goto gp_fault; + rdmsrl(MSR_IA32_PLATFORM_ID, *val); + break; + case MSR_AMD_PATCHLEVEL: BUILD_BUG_ON(MSR_IA32_UCODE_REV != MSR_AMD_PATCHLEVEL); /* @@ -275,6 +282,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) { uint64_t rsvd; + case MSR_IA32_PLATFORM_ID: case MSR_INTEL_CORE_THREAD_COUNT: case MSR_INTEL_PLATFORM_INFO: case MSR_ARCH_CAPABILITIES: |