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authorAndrew Cooper <andrew.cooper3@citrix.com>2020-09-15 12:44:01 +0200
committerJan Beulich <jbeulich@suse.com>2020-09-15 12:44:01 +0200
commit51526576219f122ec7ccfd55dea95afbca70d330 (patch)
treeb02dcc5e2d92692f77c88ce751f3f358a7e5fbb7 /xen/arch/x86/msr.c
parent84e848fd7a162f669cf8248ce502ca864f869447 (diff)
x86/msr: drop compatibility #GP handling in guest_{rd,wr}msr()
Now that the main PV/HVM MSR handlers raise #GP for all unknown MSRs, there is no need to special case these MSRs any more. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
Diffstat (limited to 'xen/arch/x86/msr.c')
-rw-r--r--xen/arch/x86/msr.c46
1 files changed, 0 insertions, 46 deletions
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 79fbb9e940..81b34fb212 100644
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -175,29 +175,6 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val)
switch ( msr )
{
- case MSR_AMD_PATCHLOADER:
- case MSR_IA32_UCODE_WRITE:
- case MSR_PRED_CMD:
- case MSR_FLUSH_CMD:
- /* Write-only */
- case MSR_TEST_CTRL:
- case MSR_CORE_CAPABILITIES:
- case MSR_TSX_FORCE_ABORT:
- case MSR_TSX_CTRL:
- case MSR_MCU_OPT_CTRL:
- case MSR_RTIT_OUTPUT_BASE ... MSR_RTIT_ADDR_B(7):
- case MSR_U_CET:
- case MSR_S_CET:
- case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE:
- case MSR_AMD64_LWP_CFG:
- case MSR_AMD64_LWP_CBADDR:
- case MSR_PPIN_CTL:
- case MSR_PPIN:
- case MSR_AMD_PPIN_CTL:
- case MSR_AMD_PPIN:
- /* Not offered to guests. */
- goto gp_fault;
-
case MSR_IA32_FEATURE_CONTROL:
if ( !cp->basic.vmx && !vmce_has_lmce(v) )
goto gp_fault;
@@ -364,29 +341,6 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val)
{
uint64_t rsvd;
- case MSR_IA32_PLATFORM_ID:
- case MSR_CORE_CAPABILITIES:
- case MSR_INTEL_CORE_THREAD_COUNT:
- case MSR_INTEL_PLATFORM_INFO:
- case MSR_ARCH_CAPABILITIES:
- /* Read-only */
- case MSR_TEST_CTRL:
- case MSR_TSX_FORCE_ABORT:
- case MSR_TSX_CTRL:
- case MSR_MCU_OPT_CTRL:
- case MSR_RTIT_OUTPUT_BASE ... MSR_RTIT_ADDR_B(7):
- case MSR_U_CET:
- case MSR_S_CET:
- case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE:
- case MSR_AMD64_LWP_CFG:
- case MSR_AMD64_LWP_CBADDR:
- case MSR_PPIN_CTL:
- case MSR_PPIN:
- case MSR_AMD_PPIN_CTL:
- case MSR_AMD_PPIN:
- /* Not offered to guests. */
- goto gp_fault;
-
case MSR_AMD_PATCHLEVEL:
BUILD_BUG_ON(MSR_IA32_UCODE_REV != MSR_AMD_PATCHLEVEL);
/*