diff options
| author | Andrew Cooper <andrew.cooper3@citrix.com> | 2020-02-21 17:56:57 +0000 |
|---|---|---|
| committer | Andrew Cooper <andrew.cooper3@citrix.com> | 2020-04-21 16:52:03 +0100 |
| commit | 4803a67114279a656a54a23cebed646da32efeb6 (patch) | |
| tree | f49724dad785cf270051a71aace777605b3b71bc /xen/arch/x86/msr.c | |
| parent | 7aacf6ac49829d8dd6242f67460f4d52d0d36503 (diff) | |
x86: Enumeration for Control-flow Enforcement Technology
The CET spec has been published and guest kernels are starting to get support.
Introduce the CPUID and MSRs, and fully block the MSRs from guest use.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Wei Liu <wl@xen.org>
Diffstat (limited to 'xen/arch/x86/msr.c')
| -rw-r--r-- | xen/arch/x86/msr.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index b4a1ab0fa6..dcacae58de 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -167,6 +167,9 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) case MSR_CORE_CAPABILITIES: case MSR_TSX_FORCE_ABORT: case MSR_TSX_CTRL: + case MSR_U_CET: + case MSR_S_CET: + case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE: case MSR_AMD64_LWP_CFG: case MSR_AMD64_LWP_CBADDR: case MSR_PPIN_CTL: @@ -324,6 +327,9 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) case MSR_TEST_CTRL: case MSR_TSX_FORCE_ABORT: case MSR_TSX_CTRL: + case MSR_U_CET: + case MSR_S_CET: + case MSR_PL0_SSP ... MSR_INTERRUPT_SSP_TABLE: case MSR_AMD64_LWP_CFG: case MSR_AMD64_LWP_CBADDR: case MSR_PPIN_CTL: |