diff options
| author | Andrew Cooper <andrew.cooper3@citrix.com> | 2019-06-19 18:16:03 +0100 |
|---|---|---|
| committer | Andrew Cooper <andrew.cooper3@citrix.com> | 2019-11-12 17:12:54 +0000 |
| commit | 070e8ce9d3ace4624bb0fa87252a516e6fb0e2ea (patch) | |
| tree | fda95cd5cd544d706382b90a0346b94e0f5a5c31 /xen/arch/x86/msr.c | |
| parent | 0cafb89ae632e17f7e047cc9ff5827a8d31b6bae (diff) | |
x86/tsx: Introduce tsx= to use MSR_TSX_CTRL when available
To protect against the TSX Async Abort speculative vulnerability, Intel have
released new microcode for affected parts which introduce the MSR_TSX_CTRL
control, which allows TSX to be turned off. This will be architectural on
future parts.
Introduce tsx= to provide a global on/off for TSX, including its enumeration
via CPUID. Provide stub virtualisation of this MSR, as it is not exposed to
guests at the moment.
VMs may have booted before microcode is loaded, or before hosts have rebooted,
and they still want to migrate freely. A VM which booted seeing TSX can
migrate safely to hosts with TSX disabled - TSX will start unconditionally
aborting, but still behave in a manner compatible with the ABI.
The guest-visible behaviour is equivalent to late loading the microcode and
setting the RTM_DISABLE bit in the course of live patching.
This is part of XSA-305 / CVE-2019-11135
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Diffstat (limited to 'xen/arch/x86/msr.c')
| -rw-r--r-- | xen/arch/x86/msr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 4698d2bba1..da504ce7ae 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -133,6 +133,7 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) case MSR_FLUSH_CMD: /* Write-only */ case MSR_TSX_FORCE_ABORT: + case MSR_TSX_CTRL: case MSR_AMD64_LWP_CFG: case MSR_AMD64_LWP_CBADDR: /* Not offered to guests. */ @@ -275,6 +276,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) case MSR_ARCH_CAPABILITIES: /* Read-only */ case MSR_TSX_FORCE_ABORT: + case MSR_TSX_CTRL: case MSR_AMD64_LWP_CFG: case MSR_AMD64_LWP_CBADDR: /* Not offered to guests. */ |