aboutsummaryrefslogtreecommitdiff
path: root/drivers/clk/bcm/clk-iproc-armpll.c
blob: d7d628214b85f40481c6a9b28c49dd858448f5f5 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
/*
 * Copyright (C) 2014 Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/clkdev.h>
#include <linux/of_address.h>

#include "clk-iproc.h"

#define IPROC_CLK_MAX_FREQ_POLICY                    0x3
#define IPROC_CLK_POLICY_FREQ_OFFSET                 0x008
#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT      8
#define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK       0x7

#define IPROC_CLK_PLLARMA_OFFSET                     0xc00
#define IPROC_CLK_PLLARMA_LOCK_SHIFT                 28
#define IPROC_CLK_PLLARMA_PDIV_SHIFT                 24
#define IPROC_CLK_PLLARMA_PDIV_MASK                  0xf
#define IPROC_CLK_PLLARMA_NDIV_INT_SHIFT             8
#define IPROC_CLK_PLLARMA_NDIV_INT_MASK              0x3ff

#define IPROC_CLK_PLLARMB_OFFSET                     0xc04
#define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK             0xfffff

#define IPROC_CLK_PLLARMC_OFFSET                     0xc08
#define IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT            8
#define IPROC_CLK_PLLARMC_MDIV_MASK                  0xff

#define IPROC_CLK_PLLARMCTL5_OFFSET                  0xc20
#define IPROC_CLK_PLLARMCTL5_H_MDIV_MASK             0xff

#define IPROC_CLK_PLLARM_OFFSET_OFFSET               0xc24
#define IPROC_CLK_PLLARM_SW_CTL_SHIFT                29
#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT       20
#define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK        0xff
#define IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK       0xfffff

#define IPROC_CLK_ARM_DIV_OFFSET                     0xe00
#define IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT  4
#define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK        0xf

#define IPROC_CLK_POLICY_DBG_OFFSET                  0xec0
#define IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT          12
#define IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK           0x7

enum iproc_arm_pll_fid {
	ARM_PLL_FID_CRYSTAL_CLK   = 0,
	ARM_PLL_FID_SYS_CLK       = 2,
	ARM_PLL_FID_CH0_SLOW_CLK  = 6,
	ARM_PLL_FID_CH1_FAST_CLK  = 7
};

struct iproc_arm_pll {
	struct clk_hw hw;
	void __iomem *base;
	unsigned long rate;
};

#define to_iproc_arm_pll(hw) container_of(hw, struct iproc_arm_pll, hw)

static unsigned int __get_fid(struct iproc_arm_pll *pll)
{
	u32 val;
	unsigned int policy, fid, active_fid;

	val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET);
	if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT))
		policy = val & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK;
	else
		policy = 0;

	/* something is seriously wrong */
	BUG_ON(policy > IPROC_CLK_MAX_FREQ_POLICY);

	val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET);
	fid = (val >> (IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT * policy)) &
		IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK;

	val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET);
	active_fid = IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK &
		(val >> IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT);
	if (fid != active_fid) {
		pr_debug("%s: fid override %u->%u\n", __func__,	fid,
				active_fid);
		fid = active_fid;
	}

	pr_debug("%s: active fid: %u\n", __func__, fid);

	return fid;
}

/*
 * Determine the mdiv (post divider) based on the frequency ID being used.
 * There are 4 sources that can be used to derive the output clock rate:
 *    - 25 MHz Crystal
 *    - System clock
 *    - PLL channel 0 (slow clock)
 *    - PLL channel 1 (fast clock)
 */
static int __get_mdiv(struct iproc_arm_pll *pll)
{
	unsigned int fid;
	int mdiv;
	u32 val;

	fid = __get_fid(pll);

	switch (fid) {
	case ARM_PLL_FID_CRYSTAL_CLK:
	case ARM_PLL_FID_SYS_CLK:
		mdiv = 1;
		break;

	case ARM_PLL_FID_CH0_SLOW_CLK:
		val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
		mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK;
		if (mdiv == 0)
			mdiv = 256;
		break;

	case ARM_PLL_FID_CH1_FAST_CLK:
		val = readl(pll->base +	IPROC_CLK_PLLARMCTL5_OFFSET);
		mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK;
		if (mdiv == 0)
			mdiv = 256;
		break;

	default:
		mdiv = -EFAULT;
	}

	return mdiv;
}

static unsigned int __get_ndiv(struct iproc_arm_pll *pll)
{
	u32 val;
	unsigned int ndiv_int, ndiv_frac, ndiv;

	val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET);
	if (val & (1 << IPROC_CLK_PLLARM_SW_CTL_SHIFT)) {
		/*
		 * offset mode is active. Read the ndiv from the PLLARM OFFSET
		 * register
		 */
		ndiv_int = (val >> IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT) &
			IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK;
		if (ndiv_int == 0)
			ndiv_int = 256;

		ndiv_frac = val & IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK;
	} else {
		/* offset mode not active */
		val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
		ndiv_int = (val >> IPROC_CLK_PLLARMA_NDIV_INT_SHIFT) &
			IPROC_CLK_PLLARMA_NDIV_INT_MASK;
		if (ndiv_int == 0)
			ndiv_int = 1024;

		val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET);
		ndiv_frac = val & IPROC_CLK_PLLARMB_NDIV_FRAC_MASK;
	}

	ndiv = (ndiv_int << 20) | ndiv_frac;

	return ndiv;
}

/*
 * The output frequency of the ARM PLL is calculated based on the ARM PLL
 * divider values:
 *   pdiv = ARM PLL pre-divider
 *   ndiv = ARM PLL multiplier
 *   mdiv = ARM PLL post divider
 *
 * The frequency is calculated by:
 *   ((ndiv * parent clock rate) / pdiv) / mdiv
 */
static unsigned long iproc_arm_pll_recalc_rate(struct clk_hw *hw,
		unsigned long parent_rate)
{
	struct iproc_arm_pll *pll = to_iproc_arm_pll(hw);
	u32 val;
	int mdiv;
	u64 ndiv;
	unsigned int pdiv;

	/* in bypass mode, use parent rate */
	val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
	if (val & (1 << IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT)) {
		pll->rate = parent_rate;
		return pll->rate;
	}

	/* PLL needs to be locked */
	val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
	if (!(val & (1 << IPROC_CLK_PLLARMA_LOCK_SHIFT))) {
		pll->rate = 0;
		return 0;
	}

	pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) &
		IPROC_CLK_PLLARMA_PDIV_MASK;
	if (pdiv == 0)
		pdiv = 16;

	ndiv = __get_ndiv(pll);
	mdiv = __get_mdiv(pll);
	if (mdiv <= 0) {
		pll->rate = 0;
		return 0;
	}
	pll->rate = (ndiv * parent_rate) >> 20;
	pll->rate = (pll->rate / pdiv) / mdiv;

	pr_debug("%s: ARM PLL rate: %lu. parent rate: %lu\n", __func__,
		 pll->rate, parent_rate);
	pr_debug("%s: ndiv_int: %u, pdiv: %u, mdiv: %d\n", __func__,
		 (unsigned int)(ndiv >> 20), pdiv, mdiv);

	return pll->rate;
}

static const struct clk_ops iproc_arm_pll_ops = {
	.recalc_rate = iproc_arm_pll_recalc_rate,
};

void __init iproc_armpll_setup(struct device_node *node)
{
	int ret;
	struct iproc_arm_pll *pll;
	struct clk_init_data init;
	const char *parent_name;

	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
	if (WARN_ON(!pll))
		return;

	pll->base = of_iomap(node, 0);
	if (WARN_ON(!pll->base))
		goto err_free_pll;

	init.name = node->name;
	init.ops = &iproc_arm_pll_ops;
	init.flags = 0;
	parent_name = of_clk_get_parent_name(node, 0);
	init.parent_names = (parent_name ? &parent_name : NULL);
	init.num_parents = (parent_name ? 1 : 0);
	pll->hw.init = &init;

	ret = clk_hw_register(NULL, &pll->hw);
	if (WARN_ON(ret))
		goto err_iounmap;

	ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll->hw);
	if (WARN_ON(ret))
		goto err_clk_unregister;

	return;

err_clk_unregister:
	clk_hw_unregister(&pll->hw);
err_iounmap:
	iounmap(pll->base);
err_free_pll:
	kfree(pll);
}