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authorAbel Vesa <abel.vesa@linaro.org>2022-10-21 21:24:02 +0300
committerAbel Vesa <abel.vesa@linaro.org>2023-01-05 15:41:46 +0200
commitf16db5e96acd2f7d5d6a3df78bbd864da579e10e (patch)
tree15ff7b63de86ffffabb2296134ebe3836c9c2a0d
parent930ce7af55dc8241aeafe2ac0573bbae704bce11 (diff)
arm64: dts: qcom: sm8550-mtp: Add PCIe PHYs and controllers nodestopic/sm8550/upstream/dts-pcie
Enable PCIe controllers and PHYs nodes on SM8550 MTP board. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
-rw-r--r--arch/arm64/boot/dts/qcom/sm8550-mtp.dts29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
index 8586e16d6079..06aa379dfc15 100644
--- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts
@@ -359,6 +359,35 @@
};
};
+&pcie_1_phy_aux_clk {
+ clock-frequency = <1000>;
+};
+
+&pcie0 {
+ wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie0_phy {
+ vdda-phy-supply = <&vreg_l1e_0p88>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ status = "okay";
+};
+
+&pcie1 {
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie1_phy {
+ vdda-phy-supply = <&vreg_l3c_0p91>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+ vdda-qref-supply = <&vreg_l1e_0p88>;
+ status = "okay";
+};
+
&pm8550_gpios {
sdc2_card_det_n: sdc2-card-det-state {
pins = "gpio12";