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authorMarcus Shawcroft <marcus.shawcroft@arm.com>2017-01-24 10:57:08 +0000
committerMarcus Shawcroft <marcus.shawcroft@arm.com>2017-01-25 08:47:22 +0000
commit762c8e0d20259258fc206ea691cb75a1abe7f107 (patch)
tree2aec430bccf166bfff82e862288c0ee734678ad0 /include/gpio.h
parentcf94f6144d31f5de1bdb2d5ef40bb45bde031f29 (diff)
gpio: Merge the OPEN_DRAIN interface with the DRIVE_STRENGTH interface.
Fold the OPEN_DRAIN GPIO interface into the DRIVE_STRENGTH interface. The latter is more flexibile, suporting a larger range of hardware capability. Change-Id: I7ee01c8d375e3e4fe8ad10c075e365d246e83c75 Signed-off-by: Marcus Shawcroft <marcus.shawcroft@arm.com>
Diffstat (limited to 'include/gpio.h')
-rw-r--r--include/gpio.h18
1 files changed, 2 insertions, 16 deletions
diff --git a/include/gpio.h b/include/gpio.h
index 36bf84be7..3d6c9b5c4 100644
--- a/include/gpio.h
+++ b/include/gpio.h
@@ -120,20 +120,6 @@ extern "C" {
/** Disable GPIO pin. */
#define GPIO_PIN_DISABLE (1 << 11)
-/** @cond INTERNAL_HIDDEN */
-#define GPIO_PP_OD_POS 12
-/** @endcond */
-
-/** Enable GPIO pin push-pull. */
-#define GPIO_PUSH_PULL (0 << GPIO_PP_OD_POS)
-
-/** Enable GPIO pin open drain. */
-#define GPIO_OPEN_DRAIN (1 << GPIO_PP_OD_POS)
-
-/** @cond INTERNAL_HIDDEN */
-#define GPIO_PP_OD_MASK (1 << GPIO_PP_OD_POS)
-/** @endcond */
-
/* GPIO_DS_* are for pin drive strength configuration.
*
* The drive strength of individual pins can be configured
@@ -161,7 +147,7 @@ extern "C" {
*/
/** @cond INTERNAL_HIDDEN */
-#define GPIO_DS_LOW_POS 13
+#define GPIO_DS_LOW_POS 12
#define GPIO_DS_LOW_MASK (0x3 << GPIO_DS_LOW_POS)
/** @endcond */
@@ -182,7 +168,7 @@ extern "C" {
#define GPIO_DS_DISCONNECT_LOW (0x3 << GPIO_DS_LOW_POS)
/** @cond INTERNAL_HIDDEN */
-#define GPIO_DS_HIGH_POS 15
+#define GPIO_DS_HIGH_POS 14
#define GPIO_DS_HIGH_MASK (0x3 << GPIO_DS_HIGH_POS)
/** @endcond */