pwm/stm32: add PWM driver for STM32 F1/F4/L4

Provide PWM driver for STM32 series F1/F4/L4.
Driver is ported on STM32Cube HAL and should support other STM32
series with minor updates.
Configuration is done so that PWM sample driver could be run on
all nucleo boards supporting PWM driver.

Change-Id: I6522a565451085df932e0eefd8404268380b5bfe
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>

5 files changed, 414 insertions, 1 deletions

diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index b8e067088..aaede520c 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -32,4 +32,6 @@ source "drivers/pwm/Kconfig.dw"
 
 source "drivers/pwm/Kconfig.k64"
 
+source "drivers/pwm/Kconfig.stm32"
+
 endif # PWM
diff --git a/drivers/pwm/Kconfig.stm32 b/drivers/pwm/Kconfig.stm32
new file mode 100644
index 000000000..386cfe546
--- /dev/null
+++ b/drivers/pwm/Kconfig.stm32
@@ -0,0 +1,56 @@
+# Kconfig.stm32 - STM32 PWM configuration options
+#
+#
+# Copyright (c) 2016 Linaro Limited.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+menuconfig PWM_STM32
+	bool "STM32 MCU PWM driver"
+	default n
+	depends on PWM && SOC_FAMILY_STM32
+	help
+	  This option enables the PWM driver for STM32 family of
+	  processors. Say y if you wish to use PWM port on STM32
+	  MCU.
+
+config PWM_STM32_1
+	bool "STM32 PWM 1 Output"
+	depends on PWM_STM32
+	default n
+	help
+	  Enable output for PWM1 in the driver. Say y here
+	  if you want to use PWM1 output.
+
+config PWM_STM32_1_DEV_NAME
+	string "STM32 PWM Device Name"
+	default "PWM_1"
+	depends on PWM_STM32_1
+	help
+	  Specify the device name for the PWM driver.
+
+config PWM_STM32_2
+	bool "STM32 PWM 2 Output"
+	depends on PWM_STM32
+	default n
+	help
+	  Enable output for PWM2 in the driver. Say y here
+	  if you want to use PWM2 output.
+
+config PWM_STM32_2_DEV_NAME
+	string "STM32 PWM Device Name"
+	default "PWM_2"
+	depends on PWM_STM32_2
+	help
+	  Specify the device name for the PWM driver.
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 2b20a9db5..b321ccae9 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -6,4 +6,4 @@ obj-$(CONFIG_PWM_PCA9685)	+= pwm_pca9685.o
 obj-$(CONFIG_PWM_DW)		+= pwm_dw.o
 obj-$(CONFIG_PWM_QMSI)		+= pwm_qmsi.o
 obj-$(CONFIG_PWM_K64_FTM)	+= pwm_k64_ftm.o
-
+obj-$(CONFIG_PWM_STM32)		+= pwm_stm32.o
diff --git a/drivers/pwm/pwm_stm32.c b/drivers/pwm/pwm_stm32.c
new file mode 100644
index 000000000..daf6c657b
--- /dev/null
+++ b/drivers/pwm/pwm_stm32.c
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <errno.h>
+
+#include <board.h>
+#include <pwm.h>
+#include <device.h>
+#include <kernel.h>
+#include <init.h>
+
+#include <clock_control/stm32_clock_control.h>
+
+#include "pwm_stm32.h"
+
+/* convenience defines */
+#define DEV_CFG(dev)							\
+	((const struct pwm_stm32_config * const)(dev)->config->config_info)
+#define DEV_DATA(dev)							\
+	((struct pwm_stm32_data * const)(dev)->driver_data)
+#define PWM_STRUCT(dev)					\
+	((TIM_TypeDef *)(DEV_CFG(dev))->pwm_base)
+
+#ifdef CONFIG_SOC_SERIES_STM32F1X
+#define CLOCK_SUBSYS_TIM1 STM32F10X_CLOCK_SUBSYS_TIM1
+#define CLOCK_SUBSYS_TIM2 STM32F10X_CLOCK_SUBSYS_TIM2
+#elif CONFIG_SOC_SERIES_STM32L4X
+#define CLOCK_SUBSYS_TIM1 STM32L4X_CLOCK_SUBSYS_TIM1
+#define CLOCK_SUBSYS_TIM2 STM32L4X_CLOCK_SUBSYS_TIM2
+#endif
+
+#define CHANNEL_LENGTH 4
+
+#ifdef CONFIG_SOC_SERIES_STM32F4X
+static uint32_t __get_tim_clk(uint32_t bus_clk,
+			      clock_control_subsys_t *sub_system)
+{
+	struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system);
+	uint32_t tim_clk, apb_psc;
+
+	if (pclken->bus == STM32F4X_CLOCK_BUS_APB1) {
+		apb_psc = CONFIG_CLOCK_STM32F4X_APB1_PRESCALER;
+	} else {
+		apb_psc = CONFIG_CLOCK_STM32F4X_APB2_PRESCALER;
+	}
+
+	if (apb_psc == RCC_HCLK_DIV1) {
+		tim_clk = bus_clk;
+	} else	{
+		tim_clk = 2 * bus_clk;
+	}
+
+	return tim_clk;
+}
+
+#else
+
+static uint32_t __get_tim_clk(uint32_t bus_clk,
+			      clock_control_subsys_t sub_system)
+{
+	uint32_t tim_clk, apb_psc;
+	uint32_t subsys = POINTER_TO_UINT(sub_system);
+
+#ifdef CONFIG_SOC_SERIES_STM32L4X
+	if (STM32L4X_CLOCK_BASE(subsys) == STM32L4X_CLOCK_APB2_BASE) {
+		apb_psc = CONFIG_CLOCK_STM32L4X_APB2_PRESCALER;
+	} else {
+		apb_psc = CONFIG_CLOCK_STM32L4X_APB1_PRESCALER;
+	}
+#elif CONFIG_SOC_SERIES_STM32F1X
+	if (subsys > STM32F10X_CLOCK_APB2_BASE) {
+		apb_psc = CONFIG_CLOCK_STM32F10X_APB2_PRESCALER;
+	} else {
+		apb_psc = CONFIG_CLOCK_STM32F10X_APB1_PRESCALER;
+	}
+#endif
+
+	if (apb_psc == RCC_HCLK_DIV1) {
+		tim_clk = bus_clk;
+	} else	{
+		tim_clk = 2 * bus_clk;
+	}
+
+	return tim_clk;
+}
+#endif /* CONFIG_SOC_SERIES_STM32F4X */
+
+/*
+ * Set the period and pulse width for a PWM pin.
+ *
+ * Parameters
+ * dev: Pointer to PWM device structure
+ * pwm: PWM channel to set
+ * period_cycles: Period (in timer count)
+ * pulse_cycles: Pulse width (in timer count).
+ *
+ * return 0, or negative errno code
+ */
+static int pwm_stm32_pin_set(struct device *dev, uint32_t pwm,
+			     uint32_t period_cycles, uint32_t pulse_cycles)
+{
+	struct pwm_stm32_data *data = DEV_DATA(dev);
+	TIM_HandleTypeDef *TimerHandle = &data->hpwm;
+	TIM_OC_InitTypeDef sConfig;
+	uint32_t channel;
+	bool counter_32b;
+
+	if (period_cycles == 0 || pulse_cycles > period_cycles) {
+		return -EINVAL;
+	}
+
+	/* configure channel */
+	channel = (pwm - 1)*CHANNEL_LENGTH;
+
+	if (!IS_TIM_INSTANCE(PWM_STRUCT(dev)) ||
+		!IS_TIM_CHANNELS(channel)) {
+		return -ENOTSUP;
+	}
+
+#ifdef CONFIG_SOC_SERIES_STM32F1X
+	/* FIXME: IS_TIM_32B_COUNTER_INSTANCE not available on
+	 * SMT32F1 Cube HAL since all timer counters are 16 bits
+	 */
+	counter_32b = 0;
+#else
+	counter_32b = IS_TIM_32B_COUNTER_INSTANCE(PWM_STRUCT(dev));
+#endif
+
+	if (!counter_32b && (period_cycles > 0xFFFF)) {
+		/* 16 bits counter does not support requested period
+		 * You might want to adapt PWM output clock to adjust
+		 * cycle durations to fit requested period into 16 bits
+		 * counter
+		 */
+		return -ENOTSUP;
+	}
+
+	/* Configure Timer IP */
+	TimerHandle->Instance = PWM_STRUCT(dev);
+	TimerHandle->Init.Prescaler = data->pwm_prescaler;
+	TimerHandle->Init.ClockDivision = 0;
+	TimerHandle->Init.CounterMode = TIM_COUNTERMODE_UP;
+	TimerHandle->Init.RepetitionCounter = 0;
+
+	/* Set period value */
+	TimerHandle->Init.Period = period_cycles;
+
+	HAL_TIM_PWM_Init(TimerHandle);
+
+	/* Configure PWM channel */
+	sConfig.OCMode       = TIM_OCMODE_PWM1;
+	sConfig.OCPolarity   = TIM_OCPOLARITY_HIGH;
+	sConfig.OCFastMode   = TIM_OCFAST_DISABLE;
+	sConfig.OCNPolarity  = TIM_OCNPOLARITY_HIGH;
+	sConfig.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+	sConfig.OCIdleState  = TIM_OCIDLESTATE_RESET;
+
+	/* Set the pulse value */
+	sConfig.Pulse = pulse_cycles;
+
+	HAL_TIM_PWM_ConfigChannel(TimerHandle, &sConfig, channel);
+
+	return HAL_TIM_PWM_Start(TimerHandle, channel);
+}
+
+/*
+ * Get the clock rate (cycles per second) for a PWM pin.
+ *
+ * Parameters
+ * dev: Pointer to PWM device structure
+ * pwm: PWM port number
+ * cycles: Pointer to the memory to store clock rate (cycles per second)
+ *
+ * return 0, or negative errno code
+ */
+static int pwm_stm32_get_cycles_per_sec(struct device *dev, uint32_t pwm,
+					uint64_t *cycles)
+{
+	const struct pwm_stm32_config *cfg = DEV_CFG(dev);
+	struct pwm_stm32_data *data = DEV_DATA(dev);
+	uint32_t bus_clk, tim_clk;
+
+	if (cycles == NULL) {
+		return -EINVAL;
+	}
+
+	/* Timer clock depends on APB prescaler */
+#ifdef CONFIG_SOC_SERIES_STM32F4X
+	clock_control_get_rate(data->clock,
+			(clock_control_subsys_t *)&cfg->pclken, &bus_clk);
+
+	tim_clk = __get_tim_clk(bus_clk,
+			(clock_control_subsys_t *)&cfg->pclken);
+#else
+	clock_control_get_rate(data->clock, cfg->clock_subsys, &bus_clk);
+
+	tim_clk = __get_tim_clk(bus_clk, cfg->clock_subsys);
+#endif
+
+	*cycles = (uint64_t)(tim_clk / (data->pwm_prescaler + 1));
+
+	return 0;
+}
+
+static const struct pwm_driver_api pwm_stm32_drv_api_funcs = {
+	.pin_set = pwm_stm32_pin_set,
+	.get_cycles_per_sec = pwm_stm32_get_cycles_per_sec,
+};
+
+
+static inline void __pwm_stm32_get_clock(struct device *dev)
+{
+	struct pwm_stm32_data *data = DEV_DATA(dev);
+	struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
+
+	__ASSERT_NO_MSG(clk);
+
+	data->clock = clk;
+}
+
+
+static int pwm_stm32_init(struct device *dev)
+{
+	const struct pwm_stm32_config *config = DEV_CFG(dev);
+	struct pwm_stm32_data *data = DEV_DATA(dev);
+
+	__pwm_stm32_get_clock(dev);
+
+	/* enable clock */
+#ifdef CONFIG_SOC_SERIES_STM32F4X
+	clock_control_on(data->clock,
+			(clock_control_subsys_t *)&config->pclken);
+#else
+	clock_control_on(data->clock, config->clock_subsys);
+#endif
+
+	return 0;
+}
+
+
+#ifdef CONFIG_PWM_STM32_1
+static struct pwm_stm32_data pwm_stm32_dev_data_1 = {
+	/* Default case */
+	.pwm_prescaler = 10000,
+};
+
+static const struct pwm_stm32_config pwm_stm32_dev_cfg_1 = {
+	.pwm_base = TIM1_BASE,
+#ifdef CONFIG_SOC_SERIES_STM32F4X
+	.pclken = { .bus = STM32F4X_CLOCK_BUS_APB2,
+		    .enr = STM32F4X_CLOCK_ENABLE_TIM1 },
+#else
+	.clock_subsys = UINT_TO_POINTER(CLOCK_SUBSYS_TIM1),
+#endif	/* CONFIG_SOC_SERIES_STM32F4X */
+};
+
+DEVICE_AND_API_INIT(pwm_stm32_1, CONFIG_PWM_STM32_1_DEV_NAME,
+		    pwm_stm32_init,
+		    &pwm_stm32_dev_data_1, &pwm_stm32_dev_cfg_1,
+		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
+		    &pwm_stm32_drv_api_funcs);
+#endif /* CONFIG_PWM_STM32_1 */
+
+
+#ifdef CONFIG_PWM_STM32_2
+static struct pwm_stm32_data pwm_stm32_dev_data_2 = {
+	/* Default case */
+	.pwm_prescaler = 0,
+};
+
+static const struct pwm_stm32_config pwm_stm32_dev_cfg_2 = {
+	.pwm_base = TIM2_BASE,
+#ifdef CONFIG_SOC_SERIES_STM32F4X
+	.pclken = { .bus = STM32F4X_CLOCK_BUS_APB1,
+		    .enr = STM32F4X_CLOCK_ENABLE_TIM2 },
+#else
+	.clock_subsys = UINT_TO_POINTER(CLOCK_SUBSYS_TIM2),
+#endif	/* CONFIG_SOC_SERIES_STM32F4X */
+};
+
+DEVICE_AND_API_INIT(pwm_stm32_2, CONFIG_PWM_STM32_2_DEV_NAME,
+		    pwm_stm32_init,
+		    &pwm_stm32_dev_data_2, &pwm_stm32_dev_cfg_2,
+		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
+		    &pwm_stm32_drv_api_funcs);
+#endif /* CONFIG_PWM_STM32_2 */
diff --git a/drivers/pwm/pwm_stm32.h b/drivers/pwm/pwm_stm32.h
new file mode 100644
index 000000000..e7a1972fb
--- /dev/null
+++ b/drivers/pwm/pwm_stm32.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2016 Linaro Limited.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**
+ * @file Header file for the STM32 PWM driver.
+ */
+
+#ifndef __PWM_STM32_H__
+#define __PWM_STM32_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Configuration data */
+struct pwm_stm32_config {
+	uint32_t pwm_base;
+	/* clock subsystem driving this peripheral */
+#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32L4X)
+	clock_control_subsys_t clock_subsys;
+#elif defined(CONFIG_SOC_SERIES_STM32F4X)
+	struct stm32f4x_pclken pclken;
+#endif
+};
+
+/** Runtime driver data */
+struct pwm_stm32_data {
+	/* PWM peripheral handler */
+	TIM_HandleTypeDef hpwm;
+	/* Prescaler for PWM output clock
+	 * Value used to divide the TIM clock.
+	 * Min = 0x0000U, Max = 0xFFFFU
+	 */
+	uint32_t pwm_prescaler;
+	/* clock device */
+	struct device *clock;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_STM32_H__ */