spi: restructure kconfig options

() Moves config options for each controllers into their own
   Kconfig files. This keeps upper level Kconfig from getting
   too big.
() Options for each controller are moved under their own
   submenus.

Origin: refactored from existing file
Change-Id: I813694f26126b43523b08ebdb0a5383edd241cda
Signed-off-by: Daniel Leung <daniel.leung@intel.com>

5 files changed, 730 insertions, 637 deletions

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 0e9489e9f..deb548cb4 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -1,7 +1,7 @@
 # Kconfig - SPI driver configuration options
 
 #
-# Copyright (c) 2015 Intel Corporation
+# Copyright (c) 2015-2016 Intel Corporation
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -35,644 +35,12 @@ config  SPI_DEBUG
 	help
 	  Enable debug output for SPI drivers
 
-config  SPI_INTEL
-	bool
-	prompt "Intel SPI controller driver"
-	depends on SPI && CPU_MINUTEIA
-	default n
-	help
-	  Enable support for Intel's SPI controllers. Such controller
-	  was formelly found on XScale chips. It can be found nowadays
-	  on CEXXXX Intel media controller and Quark CPU (2 of them).
-
-choice
-depends on SPI_INTEL
-prompt "Intel SPI interrupt trigger condition"
-default SPI_INTEL_RISING_EDGE
-
-config SPI_INTEL_FALLING_EDGE
-	bool "Falling edge"
-	help
-	  "Intel SPI uses falling edge interrupt"
-
-config SPI_INTEL_RISING_EDGE
-	bool "Rising edge"
-	help
-	  "Intel SPI uses rising edge interrupt"
-
-config SPI_INTEL_LEVEL_HIGH
-	bool "Level high"
-	help
-	  "Intel SPI uses level high interrupt"
-
-config SPI_INTEL_LEVEL_LOW
-	bool "Level low"
-	help
-	  "Intel SPI uses level low interrupt"
-endchoice
-
-config	SPI_INTEL_VENDOR_ID
-	hex "PCI Vendor ID"
-	depends on SPI_INTEL && PCI
-	default 0x8086
-
-config	SPI_INTEL_DEVICE_ID
-	hex "PCI Device ID"
-	depends on SPI_INTEL && PCI
-	default 0x935
-
-config	SPI_INTEL_CLASS
-	hex "PCI class"
-	depends on SPI_INTEL && PCI
-	default 0x0C
-
-config  SPI_INTEL_CS_GPIO
-	bool "SPI port CS pin is controlled via a GPIO port"
-	depends on SPI_INTEL && GPIO
-	default n
-
-config SPI_INTEL_INIT_PRIORITY
-	int
-	prompt "Init priority"
-	depends on SPI_INTEL
-	default 60
-	help
-	  Device driver initialization priority.
-
-config	SPI_INTEL_PORT_0
-	bool
-	prompt "Intel SPI port 0"
-	depends on SPI_INTEL
-	default n
-	help
-	  Enable Intel's SPI controller port 0.
-
-config  SPI_INTEL_PORT_0_DRV_NAME
-	string
-	prompt "Intel SPI port 0 device name"
-	depends on SPI_INTEL_PORT_0
-	default "SPI_0"
-
-config	SPI_INTEL_PORT_0_BUS
-	int "Port 0 PCI Bus"
-	depends on SPI_INTEL_PORT_0 && PCI
-
-config  SPI_INTEL_PORT_0_DEV
-	int "Port 0 PCI Dev"
-	depends on SPI_INTEL_PORT_0 && PCI
-
-config  SPI_INTEL_PORT_0_FUNCTION
-	int "Port 0 PCI function"
-	depends on SPI_INTEL_PORT_0 && PCI
-
-config  SPI_INTEL_PORT_0_REGS
-	hex
-	prompt "Port 0 registers address"
-	depends on SPI_INTEL_PORT_0
-
-config  SPI_INTEL_PORT_0_IRQ
-	int
-	prompt "Port 0 interrupt"
-	depends on SPI_INTEL_PORT_0
-
-config  SPI_INTEL_PORT_0_PRI
-	int
-	prompt "Port 0 interrupt priority"
-	depends on SPI_INTEL_PORT_0
-
-config  SPI_INTEL_PORT_0_CS_GPIO_PORT
-	string
-	prompt "The GPIO port which is used to control CS"
-	depends on SPI_INTEL_PORT_0 && SPI_INTEL_CS_GPIO
-	default GPIO_DW_0_NAME
-
-config  SPI_INTEL_PORT_0_CS_GPIO_PIN
-	int "The GPIO PIN which is used to act as a CS pin"
-	depends on SPI_INTEL_PORT_0 && SPI_INTEL_CS_GPIO
-	default 0
-
-config  SPI_INTEL_PORT_1
-	bool
-	prompt "Intel SPI port 1"
-	depends on SPI_INTEL
-	default n
-	help
-	  Enable Intel's SPI controller port 1.
-
-config  SPI_INTEL_PORT_1_DRV_NAME
-	string
-	prompt "Intel SPI port 1 device name"
-	depends on SPI_INTEL_PORT_1
-	default "SPI_1"
-
-config	SPI_INTEL_PORT_1_BUS
-	int "Port 1 PCI Bus"
-	depends on SPI_INTEL_PORT_1 && PCI
-
-config  SPI_INTEL_PORT_1_DEV
-	int "Port 1 PCI Dev"
-	depends on SPI_INTEL_PORT_1 && PCI
-
-config  SPI_INTEL_PORT_1_FUNCTION
-	int "Port 1 PCI function"
-	depends on SPI_INTEL_PORT_1 && PCI
-
-config  SPI_INTEL_PORT_1_REGS
-	hex
-	prompt "Port 1 registers address"
-	depends on SPI_INTEL_PORT_1
-
-config  SPI_INTEL_PORT_1_IRQ
-	int
-	prompt "Port 1 interrupt"
-	depends on SPI_INTEL_PORT_1
-
-config  SPI_INTEL_PORT_1_PRI
-	int
-	prompt "Port 0 interrupt priority"
-	depends on SPI_INTEL_PORT_1
-
-config  SPI_INTEL_PORT_1_CS_GPIO_PORT
-	string
-	prompt "The GPIO port which is used to control CS"
-	depends on SPI_INTEL_PORT_1 && SPI_INTEL_CS_GPIO
-	default GPIO_DW_0_NAME
-
-config  SPI_INTEL_PORT_1_CS_GPIO_PIN
-	int "The GPIO PIN which is used to act as a CS pin"
-	depends on SPI_INTEL_PORT_1 && SPI_INTEL_CS_GPIO
-	default 0
-
-config SPI_DW
-	bool
-	prompt "Designware SPI controller driver"
-	depends on SPI
-	default n
-	help
-	  Enable support for Designware's SPI controllers.
-
-config SPI_DW_ARC_AUX_REGS
-	bool "Registers are part of ARC auxiliary registers"
-	depends on SPI_DW && ARC
-	default y
-	help
-	  SPI IP block registers are part of user extended auxiliary
-	  registers and thus their access is different than memory
-	  mapped registers.
-
-config SPI_DW_CS_GPIO
-	bool "SPI port CS pin is controlled via a GPIO port"
-	depends on SPI_DW && GPIO
-	default n
-
-config SPI_DW_INIT_PRIORITY
-	int "Init priority"
-	depends on SPI_DW
-	default 60
-	help
-	  Device driver initialization priority.
-
-choice
-depends on SPI_DW && (IOAPIC || MVIC)
-prompt "DesignWare SPI interrupt trigger condition"
-default SPI_DW_RISING_EDGE
-
-config SPI_DW_FALLING_EDGE
-	bool "Falling edge"
-	help
-	  "DesignWare SPI uses falling edge interrupt"
-
-config SPI_DW_RISING_EDGE
-	bool "Rising edge"
-	help
-	  "DesignWare SPI uses rising edge interrupt"
-
-config SPI_DW_LEVEL_HIGH
-	bool "Level high"
-	help
-	  "DesignWare SPI uses level high interrupt"
-
-config SPI_DW_LEVEL_LOW
-	bool "Level low"
-	help
-	  "DesignWare SPI uses level low interrupt"
-endchoice
-
-choice
-depends on SPI_DW
-prompt "DesignWare SPI interrupt management logic"
-default SPI_DW_INTERRUPT_SINGLE_LINE
-
-config SPI_DW_INTERRUPT_SINGLE_LINE
-	bool "Single interrupt line for all interrupts"
-	help
-	  Only one line is used to trigger interrupts: RX, TX and ERROR
-	  interrupt go all through that line, undifferentiated.
-config SPI_DW_INTERRUPT_SEPARATED_LINES
-	bool "One line per-interrupt type (RX, TX and ERROR)"
-	help
-	  Each interrupt gets a dedicated line
-endchoice
-
-config  SPI_DW_CLOCK_GATE
-	bool "Enable glock gating"
-	depends on SPI_DW && SOC_QUARK_SE
-	select CLOCK_CONTROL
-	default n
-
-config	SPI_DW_CLOCK_GATE_DRV_NAME
-	string
-	depends on SPI_DW_CLOCK_GATE
-	default ""
-
-config	SPI_DW_PORT_0
-	bool
-	prompt "Designware SPI port 0"
-	depends on SPI_DW
-	default n
-	help
-	  Enable Designware SPI controller port 0.
-
-config  SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
-	int "Clock controller's subsystem"
-	depends on SPI_DW_CLOCK_GATE
-
-config  SPI_DW_PORT_0_CS_GPIO_PORT
-	string
-	prompt "The GPIO port which is used to control CS"
-	depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO
-	default GPIO_DW_0_NAME
-
-config  SPI_DW_PORT_0_CS_GPIO_PIN
-	int "The GPIO PIN which is used to act as a CS pin"
-	depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO
-	default 0
-
-config  SPI_DW_PORT_0_DRV_NAME
-	string
-	prompt "Designware SPI port 0 device name"
-	depends on SPI_DW_PORT_0
-	default "SPI_0"
-
-config  SPI_DW_PORT_0_REGS
-	hex
-	prompt "Port 0 registers address"
-	depends on SPI_DW_PORT_0
-
-config  SPI_DW_PORT_0_IRQ
-	int "Port 0 interrupt"
-	depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SINGLE_LINE
-	help
-	  Interrupt number dedicated to the controller. Valid if only the
-	  controller routes all interrupt through a unique line.
-
-config SPI_DW_PORT_0_ERROR_IRQ
-	int "Port 0 ERROR Interrupt"
-	depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SEPARATED_LINES
-	help
-	  Interrupt number dedicated to the ERROR interrupt only. RX and TX
-	  interrupt numbers need to be set as well.
-
-config SPI_DW_PORT_0_RX_IRQ
-	int "Port 0 RX Interrupt"
-	depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SEPARATED_LINES
-	help
-	  Interrupt number dedicated to the RX interrupt only. TX and ERROR
-	  interrupt numbers need to be set as well.
-
-config SPI_DW_PORT_0_TX_IRQ
-	int "Port 0 TX Interrupt"
-	depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SEPARATED_LINES
-	help
-	  Interrupt number dedicated to the TX interrupt only. RX and ERROR
-	  interrupt numbers need to be set as well.
-
-config  SPI_DW_PORT_0_PRI
-	int
-	prompt "Port 0 interrupt priority"
-	depends on SPI_DW_PORT_0
+source "drivers/spi/Kconfig.intel"
 
-config  SPI_DW_PORT_1
-	bool
-	prompt "Designware SPI port 1"
-	depends on SPI_DW
-	default n
-	help
-	  Enable Designware SPI controller port 1.
-
-config  SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
-	int "Clock controller's subsystem"
-	depends on SPI_DW_CLOCK_GATE
-
-config  SPI_DW_PORT_1_CS_GPIO_PORT
-	string
-	prompt "The GPIO port which is used to control CS"
-	depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO
-	default GPIO_DW_0_NAME
-
-config  SPI_DW_PORT_1_CS_GPIO_PIN
-	int "The GPIO PIN which is used to act as a CS pin"
-	depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO
-	default 0
-
-config  SPI_DW_PORT_1_DRV_NAME
-	string
-	prompt "Designware SPI port 1 device name"
-	depends on SPI_DW_PORT_1
-	default "SPI_1"
-
-config  SPI_DW_PORT_1_REGS
-	hex
-	prompt "Port 1 registers address"
-	depends on SPI_DW_PORT_1
-
-config  SPI_DW_PORT_1_IRQ
-	int "Port 1 interrupt"
-	depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SINGLE_LINE
-	help
-	  Interrupt number dedicated to the controller. Valid if only the
-	  controller routes all interrupt through a unique line.
-
-config SPI_DW_PORT_1_ERROR_IRQ
-	int "Port 1 ERROR Interrupt"
-	depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SEPARATED_LINES
-	help
-	  Interrupt number dedicated to the ERROR interrupt only. RX and TX
-	  interrupt numbers need to be set as well.
-
-config SPI_DW_PORT_1_RX_IRQ
-	int "Port 1 RX Interrupt"
-	depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SEPARATED_LINES
-	help
-	  Interrupt number dedicated to the RX interrupt only. TX and ERROR
-	  interrupt numbers need to be set as well.
-
-config SPI_DW_PORT_1_TX_IRQ
-	int "Port 1 TX Interrupt"
-	depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SEPARATED_LINES
-	help
-	  Interrupt number dedicated to the TX interrupt only. RX and ERROR
-	  interrupt numbers need to be set as well.
-
-config  SPI_DW_PORT_1_PRI
-	int
-	prompt "Port 1 interrupt priority"
-	depends on SPI_DW_PORT_1
-
-config	SPI_QMSI
-	bool "QMSI driver for SPI controller"
-	depends on SPI && QMSI_DRIVERS
-	default n
-	help
-	  SPI driver implementation using QMSI library. QMSI is the
-	  Quark Microcontroller Software Interface, providing a common
-	  interface to the Quark family of microcontrollers.
-
-config SPI_QMSI_INIT_PRIORITY
-	int
-	prompt "QMSI driver init priority"
-	depends on SPI_QMSI
-	default 60
-	help
-	  Device driver initialization priority.
-
-config	SPI_QMSI_PORT_0
-	bool
-	prompt "QMSI SPI port 0"
-	depends on SPI_QMSI
-	default n
-	help
-	  Enable QMSI's SPI controller port 0.
-
-config SPI_QMSI_CS_GPIO
-	bool "SPI port CS pin is controlled via a GPIO port"
-	depends on SPI_QMSI && GPIO
-	default n
-
-config  SPI_QMSI_PORT_0_DRV_NAME
-	string
-	prompt "QMSI SPI port 0 device name"
-	depends on SPI_QMSI_PORT_0
-	default "SPI_0"
-
-config  SPI_QMSI_PORT_0_IRQ
-	int
-	prompt "Port 0 interrupt"
-	depends on SPI_QMSI_PORT_0
-
-config  SPI_QMSI_PORT_0_PRI
-	int
-	prompt "Port 0 interrupt priority"
-	depends on SPI_QMSI_PORT_0
-
-config  SPI_QMSI_PORT_0_CS_GPIO_PORT
-	string
-	prompt "The GPIO port which is used to control CS"
-	depends on SPI_QMSI_PORT_0 && SPI_QMSI_CS_GPIO
-	default GPIO_QMSI_0_NAME
-
-config  SPI_QMSI_PORT_0_CS_GPIO_PIN
-	int "The GPIO PIN which is used to act as a CS pin"
-	depends on SPI_QMSI_PORT_0 && SPI_QMSI_CS_GPIO
-	default 0
-
-config  SPI_QMSI_PORT_1
-	bool
-	prompt "QMSI SPI port 1"
-	depends on SPI_QMSI
-	default n
-	help
-	  Enable QMSI's SPI controller port 1.
-
-config  SPI_QMSI_PORT_1_DRV_NAME
-	string
-	prompt "QMSI SPI port 1 device name"
-	depends on SPI_QMSI_PORT_1
-	default "SPI_1"
-
-config  SPI_QMSI_PORT_1_IRQ
-	int
-	prompt "Port 1 interrupt"
-	depends on SPI_QMSI_PORT_1
-
-config  SPI_QMSI_PORT_1_PRI
-	int
-	prompt "Port 0 interrupt priority"
-	depends on SPI_QMSI_PORT_1
-
-config  SPI_QMSI_PORT_1_CS_GPIO_PORT
-	string
-	prompt "The GPIO port which is used to control CS"
-	depends on SPI_QMSI_PORT_1 && SPI_QMSI_CS_GPIO
-	default GPIO_QMSI_0_NAME
-
-config  SPI_QMSI_PORT_1_CS_GPIO_PIN
-	int "The GPIO PIN which is used to act as a CS pin"
-	depends on SPI_QMSI_PORT_1 && SPI_QMSI_CS_GPIO
-	default 0
-
-config SPI_K64
-	bool
-	prompt "Freescale K64-based SPI controller driver"
-	depends on SPI
-	default n
-	help
-	  Enable support for Freescale K64-based SPI controllers.
-
-config SPI_K64_0
-	bool "Freescale K64-based SPI Module 0"
-	depends on SPI_K64
-	default n
-	help
-	  Enable config options for Freescale K64-based SPI Module 0.
-
-config SPI_K64_0_DEV_NAME
-	string "Freescale K64-based SPI Module 0 device name"
-	depends on SPI_K64_0
-	default "SPI_K64_0"
-	help
-	  Specify the device name.
-
-config SPI_K64_0_BASE_ADDR
-	hex "Freescale K64-based SPI Module 0 base address"
-	depends on SPI_K64_0
-	default 0x4002C000
-
-config SPI_K64_0_PCS_NUM
-	int "Freescale K64-based SPI Module 0 peripheral chip selects"
-	depends on SPI_K64_0
-	default 6
-	help
-	  Number of peripheral chip selects for K64 SPI Module 0
-
-config SPI_K64_0_CLK_GATE_REG_ADDR
-	hex "Freescale K64-based SPI Module 0 clock gate register address"
-	depends on SPI_K64_0
-	default 0x4004803C
+source "drivers/spi/Kconfig.dw"
 
-config SPI_K64_0_CLK_GATE_REG_BIT
-	int "Freescale K64-based SPI Module 0 clock gate register bit"
-	depends on SPI_K64_0
-	default 12
-	help
-	  Bit position enable bit in the clock gate register for K64 SPI Module 0
+source "drivers/spi/Kconfig.qmsi"
 
-config SPI_K64_0_IRQ
-	int "Freescale K64-based SPI Module 0 interrupt number"
-	depends on SPI_K64_0
-	default 26
-	help
-	  K64 SPI Module 0 IRQ number for the interrupt controller
-
-config SPI_K64_0_PRI
-	int "Freescale K64-based SPI Module 0 interrupt priority"
-	depends on SPI_K64_0
-	default 2
-	help
-	  K64 SPI Module 0 IRQ priority
-
-config SPI_K64_1
-	bool "Freescale K64-based SPI Module 1"
-	depends on SPI_K64
-	default n
-	help
-	  Enable config options for Freescale K64-based SPI Module 1.
-
-config SPI_K64_1_DEV_NAME
-	string "Freescale K64-based SPI Module 1 device name"
-	depends on SPI_K64_1
-	default "SPI_K64_1"
-	help
-	  Specify the device name.
-
-config SPI_K64_1_BASE_ADDR
-	hex "Freescale K64-based SPI Module 1 base address"
-	depends on SPI_K64_1
-	default 0x4002D000
-
-config SPI_K64_1_PCS_NUM
-	int "Freescale K64-based SPI Module 1 peripheral chip selects"
-	depends on SPI_K64_1
-	default 4
-	help
-	  Number of peripheral chip selects for K64 SPI Module 1
-
-config SPI_K64_1_CLK_GATE_REG_ADDR
-	hex "Freescale K64-based SPI Module 1 clock gate register address"
-	depends on SPI_K64_1
-	default 0x4004803C
-
-config SPI_K64_1_CLK_GATE_REG_BIT
-	int "Freescale K64-based SPI Module 0 clock gate register bit"
-	depends on SPI_K64_1
-	default 13
-	help
-	  Bit position enable bit in the clock gate register for K64 SPI Module 1
-
-config SPI_K64_1_IRQ
-	int "Freescale K64-based SPI Module 1 interrupt number"
-	depends on SPI_K64_1
-	default 27
-	help
-	  K64 SPI Module 1 IRQ number for the interrupt controller
-
-config SPI_K64_1_PRI
-	int "Freescale K64-based SPI Module 1 interrupt priority"
-	depends on SPI_K64_1
-	default 2
-	help
-	  K64 SPI Module 1 IRQ priority
-
-config SPI_K64_2
-	bool "Freescale K64-based SPI Module 2"
-	depends on SPI_K64
-	default n
-	help
-	  Enable config options for Freescale K64-based SPI Module 2.
-
-config SPI_K64_2_DEV_NAME
-	string "Freescale K64-based SPI Module 2 device name"
-	depends on SPI_K64_2
-	default "SPI_K64_2"
-	help
-	  Specify the device name.
-
-config SPI_K64_2_BASE_ADDR
-	hex "Freescale K64-based SPI Module 2 base address"
-	depends on SPI_K64_2
-	default 0x400AC000
-
-config SPI_K64_2_PCS_NUM
-	int "Freescale K64-based SPI Module 2 peripheral chip selects"
-	depends on SPI_K64_2
-	default 2
-	help
-	  Number of peripheral chip selects for K64 SPI Module 2
-
-config SPI_K64_2_CLK_GATE_REG_ADDR
-	hex "Freescale K64-based SPI Module 2 clock gate register address"
-	depends on SPI_K64_2
-	default 0x40048030
-
-config SPI_K64_2_CLK_GATE_REG_BIT
-	int "Freescale K64-based SPI Module 2 clock gate register bit"
-	depends on SPI_K64_2
-	default 12
-	help
-	  Bit position enable bit in the clock gate register for K64 SPI Module 2
-
-config SPI_K64_2_IRQ
-	int "Freescale K64-based SPI Module 2 interrupt number"
-	depends on SPI_K64_2
-	default 65
-	help
-	  K64 SPI Module 2 IRQ number for the interrupt controller
-
-config SPI_K64_2_PRI
-	int "Freescale K64-based SPI Module 2 interrupt priority"
-	depends on SPI_K64_2
-	default 2
-	help
-	  K64 SPI Module 0 IRQ priority
+source "drivers/spi/Kconfig.k64"
 
 endif # SPI
diff --git a/drivers/spi/Kconfig.dw b/drivers/spi/Kconfig.dw
new file mode 100644
index 000000000..4f5569f14
--- /dev/null
+++ b/drivers/spi/Kconfig.dw
@@ -0,0 +1,237 @@
+# Kconfig.dw - DesignWare SPI driver configuration options
+#
+#
+# Copyright (c) 2015-2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+menuconfig SPI_DW
+	bool
+	prompt "Designware SPI controller driver"
+	depends on SPI
+	default n
+	help
+	  Enable support for Designware's SPI controllers.
+
+if SPI_DW
+
+config SPI_DW_ARC_AUX_REGS
+	bool "Registers are part of ARC auxiliary registers"
+	depends on SPI_DW && ARC
+	default y
+	help
+	  SPI IP block registers are part of user extended auxiliary
+	  registers and thus their access is different than memory
+	  mapped registers.
+
+config SPI_DW_CS_GPIO
+	bool "SPI port CS pin is controlled via a GPIO port"
+	depends on SPI_DW && GPIO
+	default n
+
+config SPI_DW_INIT_PRIORITY
+	int "Init priority"
+	depends on SPI_DW
+	default 60
+	help
+	  Device driver initialization priority.
+
+choice
+depends on SPI_DW && (IOAPIC || MVIC)
+prompt "DesignWare SPI interrupt trigger condition"
+default SPI_DW_RISING_EDGE
+
+config SPI_DW_FALLING_EDGE
+	bool "Falling edge"
+	help
+	  "DesignWare SPI uses falling edge interrupt"
+
+config SPI_DW_RISING_EDGE
+	bool "Rising edge"
+	help
+	  "DesignWare SPI uses rising edge interrupt"
+
+config SPI_DW_LEVEL_HIGH
+	bool "Level high"
+	help
+	  "DesignWare SPI uses level high interrupt"
+
+config SPI_DW_LEVEL_LOW
+	bool "Level low"
+	help
+	  "DesignWare SPI uses level low interrupt"
+endchoice
+
+choice
+depends on SPI_DW
+prompt "DesignWare SPI interrupt management logic"
+default SPI_DW_INTERRUPT_SINGLE_LINE
+
+config SPI_DW_INTERRUPT_SINGLE_LINE
+	bool "Single interrupt line for all interrupts"
+	help
+	  Only one line is used to trigger interrupts: RX, TX and ERROR
+	  interrupt go all through that line, undifferentiated.
+config SPI_DW_INTERRUPT_SEPARATED_LINES
+	bool "One line per-interrupt type (RX, TX and ERROR)"
+	help
+	  Each interrupt gets a dedicated line
+endchoice
+
+config  SPI_DW_CLOCK_GATE
+	bool "Enable glock gating"
+	depends on SPI_DW && SOC_QUARK_SE
+	select CLOCK_CONTROL
+	default n
+
+config	SPI_DW_CLOCK_GATE_DRV_NAME
+	string
+	depends on SPI_DW_CLOCK_GATE
+	default ""
+
+config	SPI_DW_PORT_0
+	bool
+	prompt "Designware SPI port 0"
+	depends on SPI_DW
+	default n
+	help
+	  Enable Designware SPI controller port 0.
+
+config  SPI_DW_PORT_0_CLOCK_GATE_SUBSYS
+	int "Clock controller's subsystem"
+	depends on SPI_DW_CLOCK_GATE
+
+config  SPI_DW_PORT_0_CS_GPIO_PORT
+	string
+	prompt "The GPIO port which is used to control CS"
+	depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO
+	default GPIO_DW_0_NAME
+
+config  SPI_DW_PORT_0_CS_GPIO_PIN
+	int "The GPIO PIN which is used to act as a CS pin"
+	depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO
+	default 0
+
+config  SPI_DW_PORT_0_DRV_NAME
+	string
+	prompt "Designware SPI port 0 device name"
+	depends on SPI_DW_PORT_0
+	default "SPI_0"
+
+config  SPI_DW_PORT_0_REGS
+	hex
+	prompt "Port 0 registers address"
+	depends on SPI_DW_PORT_0
+
+config  SPI_DW_PORT_0_IRQ
+	int "Port 0 interrupt"
+	depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SINGLE_LINE
+	help
+	  Interrupt number dedicated to the controller. Valid if only the
+	  controller routes all interrupt through a unique line.
+
+config SPI_DW_PORT_0_ERROR_IRQ
+	int "Port 0 ERROR Interrupt"
+	depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SEPARATED_LINES
+	help
+	  Interrupt number dedicated to the ERROR interrupt only. RX and TX
+	  interrupt numbers need to be set as well.
+
+config SPI_DW_PORT_0_RX_IRQ
+	int "Port 0 RX Interrupt"
+	depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SEPARATED_LINES
+	help
+	  Interrupt number dedicated to the RX interrupt only. TX and ERROR
+	  interrupt numbers need to be set as well.
+
+config SPI_DW_PORT_0_TX_IRQ
+	int "Port 0 TX Interrupt"
+	depends on SPI_DW_PORT_0 && SPI_DW_INTERRUPT_SEPARATED_LINES
+	help
+	  Interrupt number dedicated to the TX interrupt only. RX and ERROR
+	  interrupt numbers need to be set as well.
+
+config  SPI_DW_PORT_0_PRI
+	int
+	prompt "Port 0 interrupt priority"
+	depends on SPI_DW_PORT_0
+
+config  SPI_DW_PORT_1
+	bool
+	prompt "Designware SPI port 1"
+	depends on SPI_DW
+	default n
+	help
+	  Enable Designware SPI controller port 1.
+
+config  SPI_DW_PORT_1_CLOCK_GATE_SUBSYS
+	int "Clock controller's subsystem"
+	depends on SPI_DW_CLOCK_GATE
+
+config  SPI_DW_PORT_1_CS_GPIO_PORT
+	string
+	prompt "The GPIO port which is used to control CS"
+	depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO
+	default GPIO_DW_0_NAME
+
+config  SPI_DW_PORT_1_CS_GPIO_PIN
+	int "The GPIO PIN which is used to act as a CS pin"
+	depends on SPI_DW_PORT_0 && SPI_DW_CS_GPIO
+	default 0
+
+config  SPI_DW_PORT_1_DRV_NAME
+	string
+	prompt "Designware SPI port 1 device name"
+	depends on SPI_DW_PORT_1
+	default "SPI_1"
+
+config  SPI_DW_PORT_1_REGS
+	hex
+	prompt "Port 1 registers address"
+	depends on SPI_DW_PORT_1
+
+config  SPI_DW_PORT_1_IRQ
+	int "Port 1 interrupt"
+	depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SINGLE_LINE
+	help
+	  Interrupt number dedicated to the controller. Valid if only the
+	  controller routes all interrupt through a unique line.
+
+config SPI_DW_PORT_1_ERROR_IRQ
+	int "Port 1 ERROR Interrupt"
+	depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SEPARATED_LINES
+	help
+	  Interrupt number dedicated to the ERROR interrupt only. RX and TX
+	  interrupt numbers need to be set as well.
+
+config SPI_DW_PORT_1_RX_IRQ
+	int "Port 1 RX Interrupt"
+	depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SEPARATED_LINES
+	help
+	  Interrupt number dedicated to the RX interrupt only. TX and ERROR
+	  interrupt numbers need to be set as well.
+
+config SPI_DW_PORT_1_TX_IRQ
+	int "Port 1 TX Interrupt"
+	depends on SPI_DW_PORT_1 && SPI_DW_INTERRUPT_SEPARATED_LINES
+	help
+	  Interrupt number dedicated to the TX interrupt only. RX and ERROR
+	  interrupt numbers need to be set as well.
+
+config  SPI_DW_PORT_1_PRI
+	int
+	prompt "Port 1 interrupt priority"
+	depends on SPI_DW_PORT_1
+
+endif # SPI_DW
diff --git a/drivers/spi/Kconfig.intel b/drivers/spi/Kconfig.intel
new file mode 100644
index 000000000..40e21f724
--- /dev/null
+++ b/drivers/spi/Kconfig.intel
@@ -0,0 +1,189 @@
+# Kconfig.intel - Intel SPI driver configuration options
+#
+#
+# Copyright (c) 2015-2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+menuconfig SPI_INTEL
+	bool
+	prompt "Intel SPI controller driver"
+	depends on SPI && CPU_MINUTEIA
+	default n
+	help
+	  Enable support for Intel's SPI controllers. Such controller
+	  was formelly found on XScale chips. It can be found nowadays
+	  on CEXXXX Intel media controller and Quark CPU (2 of them).
+
+if SPI_INTEL
+
+choice
+depends on SPI_INTEL
+prompt "Intel SPI interrupt trigger condition"
+default SPI_INTEL_RISING_EDGE
+
+config SPI_INTEL_FALLING_EDGE
+	bool "Falling edge"
+	help
+	  "Intel SPI uses falling edge interrupt"
+
+config SPI_INTEL_RISING_EDGE
+	bool "Rising edge"
+	help
+	  "Intel SPI uses rising edge interrupt"
+
+config SPI_INTEL_LEVEL_HIGH
+	bool "Level high"
+	help
+	  "Intel SPI uses level high interrupt"
+
+config SPI_INTEL_LEVEL_LOW
+	bool "Level low"
+	help
+	  "Intel SPI uses level low interrupt"
+endchoice
+
+config	SPI_INTEL_VENDOR_ID
+	hex "PCI Vendor ID"
+	depends on SPI_INTEL && PCI
+	default 0x8086
+
+config	SPI_INTEL_DEVICE_ID
+	hex "PCI Device ID"
+	depends on SPI_INTEL && PCI
+	default 0x935
+
+config	SPI_INTEL_CLASS
+	hex "PCI class"
+	depends on SPI_INTEL && PCI
+	default 0x0C
+
+config  SPI_INTEL_CS_GPIO
+	bool "SPI port CS pin is controlled via a GPIO port"
+	depends on SPI_INTEL && GPIO
+	default n
+
+config SPI_INTEL_INIT_PRIORITY
+	int
+	prompt "Init priority"
+	depends on SPI_INTEL
+	default 60
+	help
+	  Device driver initialization priority.
+
+config	SPI_INTEL_PORT_0
+	bool
+	prompt "Intel SPI port 0"
+	depends on SPI_INTEL
+	default n
+	help
+	  Enable Intel's SPI controller port 0.
+
+config  SPI_INTEL_PORT_0_DRV_NAME
+	string
+	prompt "Intel SPI port 0 device name"
+	depends on SPI_INTEL_PORT_0
+	default "SPI_0"
+
+config	SPI_INTEL_PORT_0_BUS
+	int "Port 0 PCI Bus"
+	depends on SPI_INTEL_PORT_0 && PCI
+
+config  SPI_INTEL_PORT_0_DEV
+	int "Port 0 PCI Dev"
+	depends on SPI_INTEL_PORT_0 && PCI
+
+config  SPI_INTEL_PORT_0_FUNCTION
+	int "Port 0 PCI function"
+	depends on SPI_INTEL_PORT_0 && PCI
+
+config  SPI_INTEL_PORT_0_REGS
+	hex
+	prompt "Port 0 registers address"
+	depends on SPI_INTEL_PORT_0
+
+config  SPI_INTEL_PORT_0_IRQ
+	int
+	prompt "Port 0 interrupt"
+	depends on SPI_INTEL_PORT_0
+
+config  SPI_INTEL_PORT_0_PRI
+	int
+	prompt "Port 0 interrupt priority"
+	depends on SPI_INTEL_PORT_0
+
+config  SPI_INTEL_PORT_0_CS_GPIO_PORT
+	string
+	prompt "The GPIO port which is used to control CS"
+	depends on SPI_INTEL_PORT_0 && SPI_INTEL_CS_GPIO
+	default GPIO_DW_0_NAME
+
+config  SPI_INTEL_PORT_0_CS_GPIO_PIN
+	int "The GPIO PIN which is used to act as a CS pin"
+	depends on SPI_INTEL_PORT_0 && SPI_INTEL_CS_GPIO
+	default 0
+
+config  SPI_INTEL_PORT_1
+	bool
+	prompt "Intel SPI port 1"
+	depends on SPI_INTEL
+	default n
+	help
+	  Enable Intel's SPI controller port 1.
+
+config  SPI_INTEL_PORT_1_DRV_NAME
+	string
+	prompt "Intel SPI port 1 device name"
+	depends on SPI_INTEL_PORT_1
+	default "SPI_1"
+
+config	SPI_INTEL_PORT_1_BUS
+	int "Port 1 PCI Bus"
+	depends on SPI_INTEL_PORT_1 && PCI
+
+config  SPI_INTEL_PORT_1_DEV
+	int "Port 1 PCI Dev"
+	depends on SPI_INTEL_PORT_1 && PCI
+
+config  SPI_INTEL_PORT_1_FUNCTION
+	int "Port 1 PCI function"
+	depends on SPI_INTEL_PORT_1 && PCI
+
+config  SPI_INTEL_PORT_1_REGS
+	hex
+	prompt "Port 1 registers address"
+	depends on SPI_INTEL_PORT_1
+
+config  SPI_INTEL_PORT_1_IRQ
+	int
+	prompt "Port 1 interrupt"
+	depends on SPI_INTEL_PORT_1
+
+config  SPI_INTEL_PORT_1_PRI
+	int
+	prompt "Port 0 interrupt priority"
+	depends on SPI_INTEL_PORT_1
+
+config  SPI_INTEL_PORT_1_CS_GPIO_PORT
+	string
+	prompt "The GPIO port which is used to control CS"
+	depends on SPI_INTEL_PORT_1 && SPI_INTEL_CS_GPIO
+	default GPIO_DW_0_NAME
+
+config  SPI_INTEL_PORT_1_CS_GPIO_PIN
+	int "The GPIO PIN which is used to act as a CS pin"
+	depends on SPI_INTEL_PORT_1 && SPI_INTEL_CS_GPIO
+	default 0
+
+endif # SPI_INTEL
diff --git a/drivers/spi/Kconfig.k64 b/drivers/spi/Kconfig.k64
new file mode 100644
index 000000000..f753a1963
--- /dev/null
+++ b/drivers/spi/Kconfig.k64
@@ -0,0 +1,186 @@
+# Kconfig.k64 - K64 SPI driver configuration options
+#
+#
+# Copyright (c) 2016 Intel Corporation
+# Copyright (c) 2016 Wind River Systems, Inc.
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+menuconfig SPI_K64
+	bool
+	prompt "Freescale K64-based SPI controller driver"
+	depends on SPI
+	default n
+	help
+	  Enable support for Freescale K64-based SPI controllers.
+
+if SPI_K64
+
+config SPI_K64_0
+	bool "Freescale K64-based SPI Module 0"
+	depends on SPI_K64
+	default n
+	help
+	  Enable config options for Freescale K64-based SPI Module 0.
+
+config SPI_K64_0_DEV_NAME
+	string "Freescale K64-based SPI Module 0 device name"
+	depends on SPI_K64_0
+	default "SPI_K64_0"
+	help
+	  Specify the device name.
+
+config SPI_K64_0_BASE_ADDR
+	hex "Freescale K64-based SPI Module 0 base address"
+	depends on SPI_K64_0
+	default 0x4002C000
+
+config SPI_K64_0_PCS_NUM
+	int "Freescale K64-based SPI Module 0 peripheral chip selects"
+	depends on SPI_K64_0
+	default 6
+	help
+	  Number of peripheral chip selects for K64 SPI Module 0
+
+config SPI_K64_0_CLK_GATE_REG_ADDR
+	hex "Freescale K64-based SPI Module 0 clock gate register address"
+	depends on SPI_K64_0
+	default 0x4004803C
+
+config SPI_K64_0_CLK_GATE_REG_BIT
+	int "Freescale K64-based SPI Module 0 clock gate register bit"
+	depends on SPI_K64_0
+	default 12
+	help
+	  Bit position enable bit in the clock gate register for K64 SPI Module 0
+
+config SPI_K64_0_IRQ
+	int "Freescale K64-based SPI Module 0 interrupt number"
+	depends on SPI_K64_0
+	default 26
+	help
+	  K64 SPI Module 0 IRQ number for the interrupt controller
+
+config SPI_K64_0_PRI
+	int "Freescale K64-based SPI Module 0 interrupt priority"
+	depends on SPI_K64_0
+	default 2
+	help
+	  K64 SPI Module 0 IRQ priority
+
+config SPI_K64_1
+	bool "Freescale K64-based SPI Module 1"
+	depends on SPI_K64
+	default n
+	help
+	  Enable config options for Freescale K64-based SPI Module 1.
+
+config SPI_K64_1_DEV_NAME
+	string "Freescale K64-based SPI Module 1 device name"
+	depends on SPI_K64_1
+	default "SPI_K64_1"
+	help
+	  Specify the device name.
+
+config SPI_K64_1_BASE_ADDR
+	hex "Freescale K64-based SPI Module 1 base address"
+	depends on SPI_K64_1
+	default 0x4002D000
+
+config SPI_K64_1_PCS_NUM
+	int "Freescale K64-based SPI Module 1 peripheral chip selects"
+	depends on SPI_K64_1
+	default 4
+	help
+	  Number of peripheral chip selects for K64 SPI Module 1
+
+config SPI_K64_1_CLK_GATE_REG_ADDR
+	hex "Freescale K64-based SPI Module 1 clock gate register address"
+	depends on SPI_K64_1
+	default 0x4004803C
+
+config SPI_K64_1_CLK_GATE_REG_BIT
+	int "Freescale K64-based SPI Module 0 clock gate register bit"
+	depends on SPI_K64_1
+	default 13
+	help
+	  Bit position enable bit in the clock gate register for K64 SPI Module 1
+
+config SPI_K64_1_IRQ
+	int "Freescale K64-based SPI Module 1 interrupt number"
+	depends on SPI_K64_1
+	default 27
+	help
+	  K64 SPI Module 1 IRQ number for the interrupt controller
+
+config SPI_K64_1_PRI
+	int "Freescale K64-based SPI Module 1 interrupt priority"
+	depends on SPI_K64_1
+	default 2
+	help
+	  K64 SPI Module 1 IRQ priority
+
+config SPI_K64_2
+	bool "Freescale K64-based SPI Module 2"
+	depends on SPI_K64
+	default n
+	help
+	  Enable config options for Freescale K64-based SPI Module 2.
+
+config SPI_K64_2_DEV_NAME
+	string "Freescale K64-based SPI Module 2 device name"
+	depends on SPI_K64_2
+	default "SPI_K64_2"
+	help
+	  Specify the device name.
+
+config SPI_K64_2_BASE_ADDR
+	hex "Freescale K64-based SPI Module 2 base address"
+	depends on SPI_K64_2
+	default 0x400AC000
+
+config SPI_K64_2_PCS_NUM
+	int "Freescale K64-based SPI Module 2 peripheral chip selects"
+	depends on SPI_K64_2
+	default 2
+	help
+	  Number of peripheral chip selects for K64 SPI Module 2
+
+config SPI_K64_2_CLK_GATE_REG_ADDR
+	hex "Freescale K64-based SPI Module 2 clock gate register address"
+	depends on SPI_K64_2
+	default 0x40048030
+
+config SPI_K64_2_CLK_GATE_REG_BIT
+	int "Freescale K64-based SPI Module 2 clock gate register bit"
+	depends on SPI_K64_2
+	default 12
+	help
+	  Bit position enable bit in the clock gate register for K64 SPI Module 2
+
+config SPI_K64_2_IRQ
+	int "Freescale K64-based SPI Module 2 interrupt number"
+	depends on SPI_K64_2
+	default 65
+	help
+	  K64 SPI Module 2 IRQ number for the interrupt controller
+
+config SPI_K64_2_PRI
+	int "Freescale K64-based SPI Module 2 interrupt priority"
+	depends on SPI_K64_2
+	default 2
+	help
+	  K64 SPI Module 0 IRQ priority
+
+endif # SPI_K64
diff --git a/drivers/spi/Kconfig.qmsi b/drivers/spi/Kconfig.qmsi
new file mode 100644
index 000000000..6a0e29526
--- /dev/null
+++ b/drivers/spi/Kconfig.qmsi
@@ -0,0 +1,113 @@
+# Kconfig.qmsi - QMSI SPI driver configuration options
+#
+#
+# Copyright (c) 2016 Intel Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+menuconfig SPI_QMSI
+	bool "QMSI driver for SPI controller"
+	depends on SPI && QMSI_DRIVERS
+	default n
+	help
+	  SPI driver implementation using QMSI library. QMSI is the
+	  Quark Microcontroller Software Interface, providing a common
+	  interface to the Quark family of microcontrollers.
+
+if SPI_QMSI
+
+config SPI_QMSI_INIT_PRIORITY
+	int
+	prompt "QMSI driver init priority"
+	depends on SPI_QMSI
+	default 60
+	help
+	  Device driver initialization priority.
+
+config	SPI_QMSI_PORT_0
+	bool
+	prompt "QMSI SPI port 0"
+	depends on SPI_QMSI
+	default n
+	help
+	  Enable QMSI's SPI controller port 0.
+
+config SPI_QMSI_CS_GPIO
+	bool "SPI port CS pin is controlled via a GPIO port"
+	depends on SPI_QMSI && GPIO
+	default n
+
+config  SPI_QMSI_PORT_0_DRV_NAME
+	string
+	prompt "QMSI SPI port 0 device name"
+	depends on SPI_QMSI_PORT_0
+	default "SPI_0"
+
+config  SPI_QMSI_PORT_0_IRQ
+	int
+	prompt "Port 0 interrupt"
+	depends on SPI_QMSI_PORT_0
+
+config  SPI_QMSI_PORT_0_PRI
+	int
+	prompt "Port 0 interrupt priority"
+	depends on SPI_QMSI_PORT_0
+
+config  SPI_QMSI_PORT_0_CS_GPIO_PORT
+	string
+	prompt "The GPIO port which is used to control CS"
+	depends on SPI_QMSI_PORT_0 && SPI_QMSI_CS_GPIO
+	default GPIO_QMSI_0_NAME
+
+config  SPI_QMSI_PORT_0_CS_GPIO_PIN
+	int "The GPIO PIN which is used to act as a CS pin"
+	depends on SPI_QMSI_PORT_0 && SPI_QMSI_CS_GPIO
+	default 0
+
+config  SPI_QMSI_PORT_1
+	bool
+	prompt "QMSI SPI port 1"
+	depends on SPI_QMSI
+	default n
+	help
+	  Enable QMSI's SPI controller port 1.
+
+config  SPI_QMSI_PORT_1_DRV_NAME
+	string
+	prompt "QMSI SPI port 1 device name"
+	depends on SPI_QMSI_PORT_1
+	default "SPI_1"
+
+config  SPI_QMSI_PORT_1_IRQ
+	int
+	prompt "Port 1 interrupt"
+	depends on SPI_QMSI_PORT_1
+
+config  SPI_QMSI_PORT_1_PRI
+	int
+	prompt "Port 0 interrupt priority"
+	depends on SPI_QMSI_PORT_1
+
+config  SPI_QMSI_PORT_1_CS_GPIO_PORT
+	string
+	prompt "The GPIO port which is used to control CS"
+	depends on SPI_QMSI_PORT_1 && SPI_QMSI_CS_GPIO
+	default GPIO_QMSI_0_NAME
+
+config  SPI_QMSI_PORT_1_CS_GPIO_PIN
+	int "The GPIO PIN which is used to act as a CS pin"
+	depends on SPI_QMSI_PORT_1 && SPI_QMSI_CS_GPIO
+	default 0
+
+endif # SPI_QMSI