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| author | Damien George <damien.p.george@gmail.com> | 2018-08-17 01:11:06 +1000 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2018-08-17 14:11:37 +1000 |
| commit | fd10a11c6bbed4c237e6f099b0161352b7913fa5 (patch) | |
| tree | 4edf0afdfed6e78759daede54942685ee7b370e5 /py/asmxtensa.h | |
| parent | f7746141106a5caa1b02c08d4e083260d2b9e1c1 (diff) | |
py/asmxtensa: Fix bug with order of regs in addi encoding.
Diffstat (limited to 'py/asmxtensa.h')
| -rw-r--r-- | py/asmxtensa.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/py/asmxtensa.h b/py/asmxtensa.h index 5198e0199..9a8ef45c0 100644 --- a/py/asmxtensa.h +++ b/py/asmxtensa.h @@ -118,7 +118,7 @@ static inline void asm_xtensa_op_add(asm_xtensa_t *as, uint reg_dest, uint reg_s } static inline void asm_xtensa_op_addi(asm_xtensa_t *as, uint reg_dest, uint reg_src, int imm8) { - asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 12, reg_dest, reg_src, imm8 & 0xff)); + asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 12, reg_src, reg_dest, imm8 & 0xff)); } static inline void asm_xtensa_op_and(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) { |