From 7cda8aba0cc1ae3404e2f37eb211eea01bc39905 Mon Sep 17 00:00:00 2001
From: never <none@none>
Date: Thu, 19 Aug 2010 14:51:47 -0700
Subject: 6978249: spill between cpu and fpu registers when those moves are
 fast Reviewed-by: kvn

---
 src/share/vm/opto/coalesce.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/share/vm/opto/coalesce.cpp')

diff --git a/src/share/vm/opto/coalesce.cpp b/src/share/vm/opto/coalesce.cpp
index 311b55a71..2144b59ec 100644
--- a/src/share/vm/opto/coalesce.cpp
+++ b/src/share/vm/opto/coalesce.cpp
@@ -780,6 +780,14 @@ bool PhaseConservativeCoalesce::copy_copy( Node *dst_copy, Node *src_copy, Block
   // Number of bits free
   uint rm_size = rm.Size();
 
+  if (UseFPUForSpilling && rm.is_AllStack() ) {
+    // Don't coalesce when frequency difference is large
+    Block *dst_b = _phc._cfg._bbs[dst_copy->_idx];
+    Block *src_def_b = _phc._cfg._bbs[src_def->_idx];
+    if (src_def_b->_freq > 10*dst_b->_freq )
+      return false;
+  }
+
   // If we can use any stack slot, then effective size is infinite
   if( rm.is_AllStack() ) rm_size += 1000000;
   // Incompatible masks, no way to coalesce
-- 
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