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Tie DIP switch DSW3-5 to the dynamic PCD that defers enabling of the
PCIe Bus Master Enable bit to the first PciIo->Map() call made by the
driver. This helps identify drivers that don't bother to use Map/Unmap
at all, which is a violation of the UEFI spec.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Enable the special non-1:1 DMA IOMMU driver into the eMMC driver and
into the second PCIe RC.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Force the use of 64-bit DMA for PCI by removing the first DRAM region,
which is the only 32-bit addressable chunk of memory available on this
platform. This forces drivers for PCIe devices to enable 64-bit DMA
addressing, which many don't bother to do since it is not usually
necessary on a x86/PC platform.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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For testing purposes, reconfigure the first PCI host bridge to only
expose a single MMIO window of 512 MB in size, and map it below 4 GB
on the PCI side (so 32-bit BARs can be allocated from it) and above
4 GB on the CPU side.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Add a missing intermediate UINTN case to fix the 32-bit build.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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When encountering memory that is above the threshold of what we can
map, don't add it to the virtual memory table. This table is only
used by the early MMU code that creates the 1:1 mapping, and since
it cannot be mapped in the first place, there is no point.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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When running on 32-bit ARM, we cannot decode the MMIO64 region, and
so we don't set the EFI_PCI_HOST_BRIDGE_MEM64_DECODE flag in this
case. However, with that flag cleared, it is no longer permitted to
include a definition for the placement of the MMIO64 region either,
so remove those as well if MDE_CPU_ARM is set (which is the same
condition under which EFI_PCI_HOST_BRIDGE_MEM64_DECODE is cleared)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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On headless server systems where the PL011 serial port is the primary
console, having DEBUG output on the same port can be annoying, since
DEBUG output gets lost when the console driver clears the screen or
positions the cursor using control characters.
So add the ability to emit the DEBUG output on the DesignWare FUART
(which is exposed via the LS connector on DeveloperBox)
Mark Kettenis <mark.kettenis@xs4all.nl> says:
The DesignWare component is (largely) 16550-compatible. But the
FIFO's are optional and if they're not included you'll end up with
something that's probably closer to an 16450. I suspect in most
cases SoC designers will include the FIFO's though since without
them you really can't use the port at anything but the slowest
speeds.
So let's use the 16550 driver in MMIO mode to drive this IP.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Give the SynQuacer NOR flash driver the same treatment as we gave the
one in ArmPlatformPkg: identify NOR flash banks by a single GUID
identifying the driver, and use indexes to identify each device instance
owned by the driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add status = "disabled" property by default for PCIe and SDHC DT nodes.
If required, update them at runtime with status = "okay". Using this
method we don't need extra DTB_PADDING.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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OP-TEE is optional on Developerbox controlled via SCP firmware. To check
if we need to enable OP-TEE DT node, we use "IsOpteePresent" OpteeLib api.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Add the basic support for enabling PCIe MMIO32 translation on the
SynQuacer, without actually enabling it just yet. It would allow us
to increase the bus range to 255 MB [from 127 MB] and the MMIO32
range to 512 MB or more [from 128 MB], but it is more likely to
cause compatibility issues with code ported from the PC platform.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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In order to allow for more flexibility when updating parts of the
firmware via capsule update, expand the description of the code FV
to cover the entire 4 MB region at the base of the NOR flash.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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In commit 913fdda9f4b9 ("Silicon/SynQuacerPlatformFlashAccessLib: don't
dereference FVB header fields"), we dropped all accesses to FVB header
field, which was necessary because the flash partition may not in fact
contain such a header. Instead, only an exact match on the base address
of the FV compared to the base address of the capsule payload would
result in a match, making it difficult to create capsules that only
update a subset of the flash contents.
Given that the FVB protocol provides a GetBlockSize() method that also
returns the number of consecutive blocks of that size, and does not rely
on the FVB header contents, we can actually infer the size of the flash
partition, and use it to decide whether a capsule payload targets an
area that is covered by this partition entirely.
This optimization allows us to extend the FV description to include the
SCP firmware partition without requiring us to actually provide a
payload for that partition immediately, which is useful as a preparatory
step.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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https://bugzilla.tianocore.org/show_bug.cgi?id=801
Add PerformFlashWriteWithProgress() to the PlatformFlashAccessLib.
This allows the platform to inform the user of progress when a
firmware storage device is being updated with a new firmware
image.
This is the minimal update to this library implementation to
keep everything building and preserve any existing progress
indication. Additional updates are required to use the
Progress() API passed into PerformFlashWriteWithProgress().
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Before adding more payload to the capsule which may be only partially
occupied, add some logic to skip writing these blocks after erasing
them.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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When we updated the capsule definition to cover the ARM Trusted Firmware
binary image as well as the firmware volume containing the EDK2 code, we
failed to recognize that the start of the image no longer constitutes a
Firmware Volume header, and so we should not interpret the data as such.
Note that this makes the FVB protocol slighty less appropriate as the
abstraction to use to write this data, but given that there does not
appear to be a better match (disk I/O, block I/O), let's stick with it
for now, but require the base address to match the capsule's target
address exactly rather than reading the size of the FV from the header.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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If no suitable FVB protocol implementation is found to apply the capsule
update, and the last one we disregarded was ruled out because it has the
read-only attribute, we will exit the function returning EFI_SUCCESS
without assigning a value to *OutFvb, resulting in a crash when it
subsequently gets dereferenced. So set the correct value for Status for
that case.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The current revision of SC2A11 contains PCIe bus issue.
In MRd transaction, 1st/Last DW BE fields are not correctly set
by hardware.
As a workaround, set TH bit and specify MSG_CODE in iATU.
With this setup, the value specified as MSG_CODE is set to the
1st/Last DW BE fields and PCIe controller can emit the correct
MRd TLP header.
Same workaround was already included for MMIO32 region,
MMIO64 region also requires this workaround.
Some deivices, such as Samsong SSD 970 EVO, do not work
without this modification.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Masahisa KOJIMA <masahisa.kojima@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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As discussed on-list [0], dynamic HII PCDs are backed by EFI variables,
but having PcdDxe DEPEXing on gEfiVariableArchProtocolGuid in general
is too restrictive, and so it is up to the platforms themselves to
DEPEX on gEfiVariableArchProtocolGuid in modules that use PCDs that
the platform may declare as dynamic HII. This also applies to the PCD
gSynQuacerTokenSpaceGuid.PcdPlatformSettings on the SynQuacer platform,
which is used by its PciHostBridgeLib implementation. So add the DEPEX
to make this dependency explicit.
[0] https://lists.01.org/pipermail/edk2-devel/2018-April/023700.html
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The ACPI/Linux code does not cope very well with I/O BAR windows that
involve type translation and address translation. In particular, the
secondary I/O window we implement on SynQuacer:
I/O 0x10000 ... 0x1ffff -> 0x77f00000
is misinterpreted by Linux, and results in the MMIO range starting at
0x77f10000 to be mapped for I/O port access to this range.
This can be mitigated by using the same bus range for I/O port access
on both RCs., i.e., [0x0 ... 0xffff]. This configuration can be represented
using both DT and ACPI, and will work as expected in Linux.
Now that the generic PCI host bridge driver has gained support for address
translation, we can actually support this configuration seamlessly in UEFI
as well, by applying an offset to the second I/O window to make it appear
adjacent to the first one in the CPU view of the I/O space.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Implement support for the SynQuacer eMMC controller. This involves an
implementation of the SD/MMC override protocol to handle a couple of
quirks that would otherwise prevent this IP from being driven by the
generic SDHCI driver.
Also, add a HII page to the PlatformDxe driver that allows eMMC support
to be enabled, and wire it up for both DeveloperBox and EVB.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Reuse the BootLogoLib graphical progress bar to show the progress of a
capsule update, and in absence of a graphical console, write a period
to the text console for each block updated.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add menu options to the SynQuacer Platform menu screen to limit the
maximum PCIe link speed for each slot individually. This may be useful
to work around potential PCIe issues.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The EVB does not boot if PCI RC #0 has no card inserted, and will hang in
the PCIe initialization code. So let's check the presence detect GPIO,
and only enable PCI RC #0 if it is asserted.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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If a PCIe RC is not enabled (due to the fact that the slot is not
populated), set its DT node 'status' property to 'disabled' so that
the OS will not attempt to attach to it.
This means we will need to switch from the default DtPlatformDtbLoaderLib
to a special one for our platform.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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In order to accommodate the EVB, whose PCIe RC #0 should not be touched
by software if no card is inserted, add a PCD that tells the PCIe driver
code which RCs should be initialized and exposed to the PCI host bridge
driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Attempt to adhere more closely to the PCIe spec by ensuring that PERST#
remains asserted for at least 100 ms. Give it a good margin, and delay
for 150 ms; the additional boot time delay is not going to be noticeable
by anyone anyway.
Add some missing barriers as well, so that the reset takes effect right
when we think it does.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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As it turns out, it is surprisingly easy to configure both the NETSEC
and eMMC devices as cache coherent for DMA, given that they are both
behind the same SMMU which is already configured in passthrough mode
by the firmware running on the SCP.
So update the static SMMU configuration to make memory accesses performed
by these devices inner shareable inner/outer writeback cacheable, which
makes them cache coherent with the CPUs.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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As it turns out, getting the PCIe controllers to switch to Gen2 speed
is surprisingly easy. It only involves setting the 'speed change' bit
in the controller at initialization time, after which the hardware
will automatically attempt to switch to Gen2 speed after training at
Gen1 speed has completed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Fix the weird indentation in the various #defines in the file containing
the RC init code. This is a whitespace only change.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The function ArmPlatformInitializeSystemMemory () has been removed from
ArmPlatformLib, so remove all the [empty] implementations provided by
the various platforms.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add the drivers, library resolutions and PCD settings to enable RTC
support on DeveloperBox. Also, update PlatformDxe to register the
non-discoverable device handles for both I2C controllers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Ordinary computers typically have a physical switch or jumper on the
board that allows non-volatile settings to be cleared. Let's implement
the same using DIP switch #1 on block #3, and clear the EFI variable
store if it is set to ON at boot time.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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In preparation of adding support for setting a DIP switch to clear the
EFI variable store, update the early capsule handling logic to take the
boot mode into account.
This is necessary for two reasons:
- we override the boot mode when a capsule is detected,
- the capsule detection itself involves reading a EFI variable, which we
shouldn't be doing if the varstore may be in a bad state.
So factor out the initial capsule check (to keep the code understandable)
and only perform it if we are not booting in 'clear NVRAM' mode.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Implement workaround suggested by Socionext to get legacy endpoints
with 32-bit BARs working. This fixes the issue on Developer Box with
the onboard ASM1061 SATA controller.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add support for dealing with capsules left in memory by the OS before
reboot. This needs to be done early, before the memory is reused, which
is why the initial handling must reside here.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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In order to support capsule update, implement PlatformFlashAccessLib that
exposes write access to the UEFI NOR partition.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Wire up the non-volatile EFI variable store support, by switching from
the emulation driver to the real one, and enabling the prerequisite
FTW and NOR flash drivers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Add the platform glue for the NOR flash driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Implement the glue library that exposes the PCIe root complexes to
the generic PCI host bridge driver. Since that driver is the first
one to access the PCI config space, put the low level init code for
the RCs into this library's constructor.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Having two distinct root complexes is not supported by the standard
set of PciLib/PciExpressLib/PciSegmentLib, so let's reimplement one
of the latter specifically for this platform (and forget about the
others).
This also allows us to implement the Synopsys Designware PCIe specific
workaround for PCI config space accesses to devices 1 and up on bus 0.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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This is a barebones port based on the .DSC/.FDF and ArmPlatformLib
code provided by Socionext. It can boot into the UiApp menu screen
or the UEFI Shell, but lacks support for any peripherals.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Implement MemoryInitPeiLib based on the newly added DramInfo
PPI, which retrieves the DRAM information from lower level
firmware.
Note that the firmware volumes in SPI NOR are mapped with
different attributes: the FV containing the PEI modules that
may execute in place is mapped as uncached memory, given that
it requires executable permissions. The FV containing the
compressed DXE modules is mapped with device attributes for
performance (!), and copied into DRAM by the platform PEIM
once permanent memory is installed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Create a specialized PlatformPeiLib implementation that invokes the
platform specific firmware interface (currently, just a data structure
left in SRAM) to set the ARM standard PcdSystemMemoryBase|Size PCDs,
and expose the information via a newly added DramInfo PPI.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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