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path: root/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi
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2017-12-12Silicon/SynQuacer: enable CPU idle states in device treeArd Biesheuvel
It appears that whatever was preventing us from using CPU idle with PSCI low power states has disappeared, so let's enable the low power states in the DT. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-12-07Silicon/SynQuacer: enable coherent DMA for NETSEC and eMMCArd Biesheuvel
As it turns out, it is surprisingly easy to configure both the NETSEC and eMMC devices as cache coherent for DMA, given that they are both behind the same SMMU which is already configured in passthrough mode by the firmware running on the SCP. So update the static SMMU configuration to make memory accesses performed by these devices inner shareable inner/outer writeback cacheable, which makes them cache coherent with the CPUs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-11-25Silicon/SynQuacer: add DT description of the SDHCI controllerArd Biesheuvel
Describe the SynQuacer SoC's eMMC controller in DT so the OS can attach to it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-11-17Silicon/SynQuacer: add description of EXIU to the device treeArd Biesheuvel
Add a DT node for the external interrupt unit (EXIU), which handles interrupts from GPIO lines. We need OS support for this for things like PHY interrupts and a 'wake' button. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-11-17Silicon/SynQuacer: add description of GPIO block to device treeArd Biesheuvel
Add a description of the SoCs GPIO controller as well as a description of DIP switch block #3, which is wired to GPIOs 0 - 7, both on the evaluation board as well as the Developer Box. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2017-11-17Silicon/SynQuacer: add device tree support for eval boardArd Biesheuvel
Add a device tree description of the SynQuacer SoC, and expose it for the SynQuacerEvalBoard platforms. This includes the menu option in the UEFI boot menu to switch between ACPI and DT. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>