diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-01-25 12:08:56 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-01-25 18:01:03 +0000 |
| commit | c76bf98bc8f988ea2f3953563f94fab8268ec3bd (patch) | |
| tree | f447b43d63de6d653b74239d56a4aa4d151fbf62 /Silicon/Socionext/SynQuacer/Library | |
| parent | 43467f4ee926acdadc1c6481a3d3407044ccc56d (diff) | |
Silicon/Socionext/SynQuacer: implement menu option to set max PCIe speed
Add menu options to the SynQuacer Platform menu screen to limit the
maximum PCIe link speed for each slot individually. This may be useful
to work around potential PCIe issues.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/Library')
2 files changed, 37 insertions, 5 deletions
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf index 27fcba03..e475529e 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf @@ -45,6 +45,7 @@ DebugLib
DevicePathLib
MemoryAllocationLib
+ PcdLib
UefiBootServicesTableLib
[FixedPcd]
@@ -52,3 +53,4 @@ [Pcd]
gSynQuacerTokenSpaceGuid.PcdPcieEnableMask
+ gSynQuacerTokenSpaceGuid.PcdPlatformSettings
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index bea40e3d..e4679543 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -18,9 +18,11 @@ #include <Library/ArmLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
#include <Library/PciHostBridgeLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Platform/Pcie.h>
+#include <Platform/VarStore.h>
#include <Protocol/PciHostBridgeResourceAllocation.h>
#define IATU_VIEWPORT_OFF 0x900
@@ -268,7 +270,8 @@ PciInitControllerPost ( IN EFI_PHYSICAL_ADDRESS DbiBase,
IN EFI_PHYSICAL_ADDRESS ConfigBase,
IN EFI_PHYSICAL_ADDRESS IoMemBase,
- IN CONST PCI_ROOT_BRIDGE *RootBridge
+ IN CONST PCI_ROOT_BRIDGE *RootBridge,
+ IN BOOLEAN EnableGen2Speed
)
{
// 4: Set Bifurcation 1=disable 4=able
@@ -312,8 +315,10 @@ PciInitControllerPost ( EFI_PCI_COMMAND_MEMORY_SPACE |
EFI_PCI_COMMAND_BUS_MASTER);
- // Force link speed change to Gen2 at link up
- MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE);
+ if (EnableGen2Speed) {
+ // Force link speed change to Gen2 at link up
+ MmioOr32 (DbiBase + GEN2_CONTROL_OFF, DIRECT_SPEED_CHANGE);
+ }
// Region 0: MMIO32 range
ConfigureWindow (DbiBase, 0,
@@ -392,7 +397,13 @@ SynQuacerPciHostBridgeLibConstructor ( IN EFI_SYSTEM_TABLE *SystemTable
)
{
- UINTN Idx;
+ UINTN Idx;
+ UINT64 SettingsVal;
+ SYNQUACER_PLATFORM_VARSTORE_DATA *Settings;
+ UINT8 MaxSpeed;
+
+ SettingsVal = PcdGet64 (PcdPlatformSettings);
+ Settings = (SYNQUACER_PLATFORM_VARSTORE_DATA *)&SettingsVal;
for (Idx = 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) {
if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) {
@@ -409,12 +420,31 @@ SynQuacerPciHostBridgeLibConstructor ( gBS->Stall (150 * 1000);
for (Idx = 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) {
+ //
+ // Check whether this root port is described by any of our 'slot'
+ // definitions, and get the maximum speed if this is the case.
+ //
+ switch (SYNQUACER_PCI_LOCATION (Idx, 0, 0)) {
+ case SYNQUACER_PCI_SLOT0_LOCATION:
+ MaxSpeed = Settings->PcieSlot0MaxSpeed;
+ break;
+ case SYNQUACER_PCI_SLOT1_LOCATION:
+ MaxSpeed = Settings->PcieSlot1MaxSpeed;
+ break;
+ case SYNQUACER_PCI_SLOT2_LOCATION:
+ MaxSpeed = Settings->PcieSlot2MaxSpeed;
+ break;
+ default:
+ MaxSpeed = PCIE_MAX_SPEED_UNLIMITED;
+ }
+
if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) {
PciInitControllerPost (mBaseAddresses[Idx].ExsBase,
mBaseAddresses[Idx].DbiBase,
mBaseAddresses[Idx].ConfigBase,
mBaseAddresses[Idx].IoMemBase,
- &mPciRootBridges[Idx]);
+ &mPciRootBridges[Idx],
+ (MaxSpeed != PCIE_MAX_SPEED_GEN1));
}
}
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