Silicon/Socionext/SynQuacer: use single translated MMIO window for PCI0

For testing purposes, reconfigure the first PCI host bridge to only
expose a single MMIO window of 512 MB in size, and map it below 4 GB
on the PCI side (so 32-bit BARs can be allocated from it) and above
4 GB on the CPU side.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

1 files changed, 1 insertions, 6 deletions

diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
index 117cf6cf..7afcec59 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
@@ -100,7 +100,7 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {
     TRUE,                                   // DmaAbove4G

     FALSE,                                  // NoExtendedConfigSpace

     FALSE,                                  // ResourceAssigned

-    PCI_ALLOCATION_ATTRIBUTES,              // AllocationAttributes

+    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM,   // AllocationAttributes

     { SYNQUACER_PCI_SEG0_BUSNUM_MIN,

       SYNQUACER_PCI_SEG0_BUSNUM_MAX },      // Bus

     { SYNQUACER_PCI_SEG0_PORTIO_MIN,

@@ -109,12 +109,7 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {
     { SYNQUACER_PCI_SEG0_MMIO32_MIN,

       SYNQUACER_PCI_SEG0_MMIO32_MAX,

       MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 },    // Mem

-#ifndef MDE_CPU_ARM

-    { SYNQUACER_PCI_SEG0_MMIO64_MIN,

-      SYNQUACER_PCI_SEG0_MMIO64_MAX },      // MemAbove4G

-#else

     { MAX_UINT64, 0x0 },                    // MemAbove4G

-#endif

     { MAX_UINT64, 0x0 },                    // PMem

     { MAX_UINT64, 0x0 },                    // PMemAbove4G

     (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]