diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-06-22 19:17:00 +0200 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-06-26 20:20:07 +0200 |
| commit | 5ed298efba3bf4a755be95c1b94224c8736719dc (patch) | |
| tree | 3cc68d795db0de2f5f387655c326cbf24dcf0fed /Silicon/Socionext/SynQuacer/Library | |
| parent | 3165d24e0c8599812bd002a04701504709d3679a (diff) | |
Silicon/SynQuacer: add preliminary support for PCIe MMIO32 translation
Add the basic support for enabling PCIe MMIO32 translation on the
SynQuacer, without actually enabling it just yet. It would allow us
to increase the bus range to 255 MB [from 127 MB] and the MMIO32
range to 512 MB or more [from 128 MB], but it is more likely to
cause compatibility issues with code ported from the PC platform.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/Library')
2 files changed, 5 insertions, 3 deletions
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c index 34193987..7c096f08 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c @@ -107,7 +107,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { SYNQUACER_PCI_SEG0_PORTIO_MAX,
MAX_UINT64 - SYNQUACER_PCI_SEG0_PORTIO_OFFSET + 1 }, // Io
{ SYNQUACER_PCI_SEG0_MMIO32_MIN,
- SYNQUACER_PCI_SEG0_MMIO32_MAX }, // Mem
+ SYNQUACER_PCI_SEG0_MMIO32_MAX,
+ MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 }, // Mem
{ SYNQUACER_PCI_SEG0_MMIO64_MIN,
SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G
{ MAX_UINT64, 0x0 }, // PMem
@@ -127,7 +128,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { SYNQUACER_PCI_SEG1_PORTIO_MAX,
MAX_UINT64 - SYNQUACER_PCI_SEG1_PORTIO_OFFSET + 1 }, // Io
{ SYNQUACER_PCI_SEG1_MMIO32_MIN,
- SYNQUACER_PCI_SEG1_MMIO32_MAX }, // Mem
+ SYNQUACER_PCI_SEG1_MMIO32_MAX,
+ MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 }, // Mem
{ SYNQUACER_PCI_SEG1_MMIO64_MIN,
SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G
{ MAX_UINT64, 0x0 }, // PMem
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index 227f9a72..75a663e9 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -322,7 +322,7 @@ PciInitControllerPost ( // Region 0: MMIO32 range
ConfigureWindow (DbiBase, 0,
- RootBridge->Mem.Base,
+ RootBridge->Mem.Base - RootBridge->Mem.Translation,
RootBridge->Mem.Base,
RootBridge->Mem.Limit - RootBridge->Mem.Base + 1,
IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM |
|