Silicon/SynQuacer: wire up non-1:1 DMA IOMMU driver

Enable the special non-1:1 DMA IOMMU driver into the eMMC driver and
into the second PCIe RC.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

3 files changed, 15 insertions, 9 deletions

diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
index fb1eb484..3d408f0e 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c
@@ -163,13 +163,21 @@ DeclareDram (
     Status = DramInfo->GetRegion (Idx, &Base, &Size);

     ASSERT_EFI_ERROR (Status);

 

+    DramDescriptor->PhysicalBase = Base;

+    DramDescriptor->Length       = MIN (Size, MAX_ALLOC_ADDRESS - Base + 1);

+    DramDescriptor->Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;

+

     if (Base < PcdGet64 (PcdSystemMemoryBase)) {

       DEBUG ((DEBUG_WARN,

-        "%a: ignoring system memory below PcdSystemMemoryBase\n",

+        "%a: remapping system memory below PcdSystemMemoryBase for non-identity mapped DMA\n",

         __FUNCTION__));

-      continue;

+      Base += FixedPcdGet64 (PcdNonIdMappedDmaOffset);

+

+      BuildMemoryAllocationHob (Base, Size, EfiReservedMemoryType);

     }

 

+    DramDescriptor->VirtualBase = Base;

+

     BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY,

       mDramResourceAttributes, Base, Size);

 

@@ -177,11 +185,6 @@ DeclareDram (
       continue;

     }

 

-    DramDescriptor->PhysicalBase = Base;

-    DramDescriptor->VirtualBase  = Base;

-    DramDescriptor->Length       = MIN (Size, MAX_ALLOC_ADDRESS - Base + 1);

-    DramDescriptor->Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;

-

     DramDescriptor++;

   }

 

diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf
index 6c3420a5..bffaac68 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf
@@ -58,6 +58,7 @@
   gFip006DxeTokenSpaceGuid.PcdFip006DxeRegBaseAddress

   gFip006DxeTokenSpaceGuid.PcdFip006DxeMemBaseAddress

   gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase

+  gSynQuacerTokenSpaceGuid.PcdNonIdMappedDmaOffset

 

 [Pcd]

   gArmTokenSpaceGuid.PcdSystemMemoryBase

diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
index 7afcec59..9ccceb6a 100644
--- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
+++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c
@@ -112,7 +112,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {
     { MAX_UINT64, 0x0 },                    // MemAbove4G

     { MAX_UINT64, 0x0 },                    // PMem

     { MAX_UINT64, 0x0 },                    // PMemAbove4G

-    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]

+    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0],

+    FALSE                                   // UseIommu

   }, {

     1,                                      // Segment

     0,                                      // Supports

@@ -137,7 +138,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = {
 #endif

     { MAX_UINT64, 0x0 },                    // PMem

     { MAX_UINT64, 0x0 },                    // PMemAbove4G

-    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]

+    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1],

+    TRUE                                    // UseIommu

   }

 };