diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2019-01-14 16:48:34 +0100 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2019-01-16 21:40:40 +0100 |
| commit | 248007cd73191289ca9b691a4626366fc8fd693c (patch) | |
| tree | 74d7659b9ba4071edb82c2ac229dab23bcf64c45 /Silicon/Socionext/SynQuacer/Library | |
| parent | 566d4bb99e702f9b2347d61491adaf3eb8031420 (diff) | |
Silicon/SynQuacerPciHostBridgeLib: fix MMIO32-only configuration
When running on 32-bit ARM, we cannot decode the MMIO64 region, and
so we don't set the EFI_PCI_HOST_BRIDGE_MEM64_DECODE flag in this
case. However, with that flag cleared, it is no longer permitted to
include a definition for the placement of the MMIO64 region either,
so remove those as well if MDE_CPU_ARM is set (which is the same
condition under which EFI_PCI_HOST_BRIDGE_MEM64_DECODE is cleared)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/Library')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c index 7c096f08..117cf6cf 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c @@ -109,8 +109,12 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { { SYNQUACER_PCI_SEG0_MMIO32_MIN,
SYNQUACER_PCI_SEG0_MMIO32_MAX,
MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 }, // Mem
+#ifndef MDE_CPU_ARM
{ SYNQUACER_PCI_SEG0_MMIO64_MIN,
SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G
+#else
+ { MAX_UINT64, 0x0 }, // MemAbove4G
+#endif
{ MAX_UINT64, 0x0 }, // PMem
{ MAX_UINT64, 0x0 }, // PMemAbove4G
(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
@@ -130,8 +134,12 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { { SYNQUACER_PCI_SEG1_MMIO32_MIN,
SYNQUACER_PCI_SEG1_MMIO32_MAX,
MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 }, // Mem
+#ifndef MDE_CPU_ARM
{ SYNQUACER_PCI_SEG1_MMIO64_MIN,
SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G
+#else
+ { MAX_UINT64, 0x0 }, // MemAbove4G
+#endif
{ MAX_UINT64, 0x0 }, // PMem
{ MAX_UINT64, 0x0 }, // PMemAbove4G
(EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
|