diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-04-16 12:57:04 +0200 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-04-26 12:06:48 +0200 |
| commit | cb16d2b5add58b25b62c3078d3c18fc0404c36e3 (patch) | |
| tree | 4c2c28f62f112d50946adf7d4bd9b48ed4e21c3f /Silicon/Socionext/SynQuacer/DeviceTree | |
| parent | 65f2f30cdaf0b14af6fb0c17c6d1fb9d3d36306e (diff) | |
Silicon/Socionext/SynQuacer: update PHY reference clock rate
As reported by Kojima-san, the PHY reference clock value we use in our
ACPI and DT descriptions is out of sync with the hardware. Replace
125 MHz with 250 MHz throughout.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Diffstat (limited to 'Silicon/Socionext/SynQuacer/DeviceTree')
| -rw-r--r-- | Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 2db7de3d..e5b5c4b9 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -420,9 +420,9 @@ reg-shift = <2>;
};
- clk_netsec: refclk125mhz {
+ clk_netsec: refclk250mhz {
compatible = "fixed-clock";
- clock-frequency = <125000000>;
+ clock-frequency = <250000000>;
#clock-cells = <0>;
};
|