diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-12-27 16:33:16 +0000 |
|---|---|---|
| committer | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-02-06 10:17:07 +0000 |
| commit | 09f94dfac187427cc9959777e7d481a56eded7e6 (patch) | |
| tree | 0922642f82a60343621cd3b3d54bc9e9e9db67b3 | |
| parent | e2a7766b739efbfb115e1d9116da04021a7ae53c (diff) | |
Silicon/SynQuacer/DeviceTree: enable PHY interruptsbuild23-09f94dfa
Enable the PHY interrupt on both the evaluation board and the
DeveloperBox board. NOTE: rev 0.1 of the DeveloperBox board lacks
a pullup in the PHY interrupt line, resulting in non-functional
Ethernet after this change.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
3 files changed, 3 insertions, 0 deletions
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts index 488c51a0..b8088647 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/DeveloperBox.dts @@ -49,5 +49,6 @@ phy_netsec: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index f1daac74..3db3c5ed 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -470,6 +470,7 @@ dma-coherent;
mdio_netsec: mdio {
+ interrupt-parent = <&exiu>;
#address-cells = <1>;
#size-cells = <0>;
};
diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts index 0c6826f5..93c45521 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts @@ -35,5 +35,6 @@ phy_netsec: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
};
};
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