diff options
| author | andrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-04-21 17:40:27 +0000 |
|---|---|---|
| committer | andrewfish <andrewfish@6f19259b-4bc3-4df7-8a09-765794883524> | 2010-04-21 17:40:27 +0000 |
| commit | 2ed3c9ccf8c056aa4df35fcd29f670ee1238fbd0 (patch) | |
| tree | 6462f458116caba4d63115068b3f2eee5de9040a /BeagleBoardPkg | |
| parent | 5efb9132d344f2393268a608f4f9737654774339 (diff) | |
Enable NEON (SIMD instructions) via coprocessor register so CopyMem/SetMem can use VLDM and friends if you want.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10386 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'BeagleBoardPkg')
| -rw-r--r-- | BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S | 8 | ||||
| -rw-r--r-- | BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm | 7 |
2 files changed, 15 insertions, 0 deletions
diff --git a/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S index 950ba43c6..07e054732 100644 --- a/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S +++ b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S @@ -35,6 +35,14 @@ ASM_PFX(_ModuleEntryPoint): orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
mcr p15, 0, r0, c1, c0, 0
+
+ // Enable NEON register in case folks want to use them for optimizations (CopyMem)
+ mrc p15, 0, r0, c1, c0, 2
+ orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
+ mcr p15, 0, r0, c1, c0, 2
+ mov r0, #0x40000000 // Set EN bit in FPEXC
+ mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly
+
// Set CPU vectors to start of DRAM
LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
diff --git a/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm index 033f03c68..d46ae2b0d 100644 --- a/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm +++ b/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm @@ -39,6 +39,13 @@ _ModuleEntryPoint orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */
mcr p15, 0, r0, c1, c0, 0
+ // Enable NEON register in case folks want to use them for optimizations (CopyMem)
+ mrc p15, 0, r0, c1, c0, 2
+ orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)
+ mcr p15, 0, r0, c1, c0, 2
+ mov r0, #0x40000000 // Set EN bit in FPEXC
+ msr FPEXC,r0
+
// Set CPU vectors to start of DRAM
LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base
mcr p15, 0, r0, c12, c0, 0
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