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authorInderpal Singh <inderpal.singh@linaro.org>2011-12-15 15:13:21 +0800
committerAndy Green <andy.green@linaro.org>2011-12-26 22:33:44 +0800
commit3803983732e79aa659ee9c9de486e0cbbc48e7f3 (patch)
tree9017be78ef17f651104a3f7f5760f7510ba5a633
parent9ca4d71ed636c4d6554fdce66995b586b130f39d (diff)
ARM: EXYNOS: Enable RTC as wake up source
Enable RTC as wake up source. Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
-rw-r--r--arch/arm/mach-exynos/cpu.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/cpu.c b/arch/arm/mach-exynos/cpu.c
index b710ac352fc..0da006c0c4a 100644
--- a/arch/arm/mach-exynos/cpu.c
+++ b/arch/arm/mach-exynos/cpu.c
@@ -38,6 +38,12 @@
#include <mach/regs-pmu.h>
#include <mach/pmu.h>
+#ifdef CONFIG_PM
+extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
+#else
+#define s3c_irq_wake NULL
+#endif
+
unsigned int gic_bank_offset __read_mostly;
extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
@@ -281,6 +287,9 @@ void __init exynos4_init_irq(void)
* uses GIC instead of VIC.
*/
s5p_init_irq(NULL, 0);
+#ifdef CONFIG_PM
+ irq_get_chip(IRQ_RTC_ALARM)->irq_set_wake = s3c_irq_wake;
+#endif
}
struct sysdev_class exynos4_sysclass = {