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/* SPDX-License-Identifier: BSD-2-Clause */
/*
* Copyright (c) 2017, Schneider Electric
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef PLATFORM_CONFIG_H
#define PLATFORM_CONFIG_H
/* GIC */
#define GIC_BASE 0x44100000
#define GIC_PPI 32
#define GICD_OFFSET 0x1000 // Offsets according to rzn1.dtsi
#define GICC_OFFSET 0x2000
#define GICD_BASE (GIC_BASE + GICD_OFFSET)
#define GICC_BASE (GIC_BASE + GICC_OFFSET)
/* UART */
#define CONSOLE_UART_BASE 0x40060000
#define CONSOLE_UART_IRQ (GIC_PPI + 6)
// The LCES memory map is designed as if there are two DRAM banks
// DRAM0 is always 128 MB, Trusted area is located at the end
// DRAM1 stand for the remaining DRAM up to the maximum
// 0x9000_0000 (DRAM1_END)-------------------+
// | U-Boot/Linux NON-SECURE 128 MB | DRAM1_SIZE
// 0x8800_0000 (DRAM1_BASE)------------------+
// | Trusted RAM (TA/TEE) SECURE 4 MB | TZDRAM_SIZE
// | Shared memory NON-SECURE 2 MB | TEE_SHMEM_SIZE
// | U-Boot/Linux NON-SECURE 122 MB |
// 0x8000_0000 (DRAM0_BASE)------------------+
// 0x2010_0000 ------------------------------+
// | Cortex-M3 NON-SECURE 400 KB |
// 0x2009_C000 ------------------------------+
// | TEE RAM: SECURE 624 KB | TZSRAM_SIZE
// 0x2000_0000 (TZRAM)-----------------------+
#define DRAM0_BASE 0x80000000
#define DRAM0_SIZE 0x08000000 // 128MB
// Available memories
#define TZDRAM_SIZE 0x00400000 // 4MB
#define TEE_SHMEM_SIZE 0x00200000 // 2MB
#define TZDRAM_BASE (DRAM0_BASE + DRAM0_SIZE - TZDRAM_SIZE)
#define TZSRAM_BASE 0x20000000
#define TZSRAM_SIZE 0x0009C000 // 624KB
#define TZDRAM_SIZE 0x00400000 // 4MB
// Choose location of TEE code
//#define TEE_RAM_START TZSRAM_BASE
#define TEE_RAM_START TZDRAM_BASE
// Configuration when TEE resides in SRAM
#if (TEE_RAM_START == TZSRAM_BASE)
#define TEE_RAM_PH_SIZE TZSRAM_SIZE
#define TEE_LOAD_ADDR (TZSRAM_BASE+0x20000) // 128KB offset
#define TA_RAM_OFFSET 0
#endif
// Configuration when TEE resides in DDR
#if (TEE_RAM_START == TZDRAM_BASE)
#define TEE_RAM_PH_SIZE 0x00100000 // 1MB
#define TEE_LOAD_ADDR TZDRAM_BASE
#define TA_RAM_OFFSET TEE_RAM_PH_SIZE
#endif
// Other TEE configuration
#define CFG_TEE_CORE_NB_CORE 2
#define TEE_RAM_VA_SIZE TEE_RAM_PH_SIZE
// TA are located in secured part (end) of DRAM0
#define TA_RAM_START (TZDRAM_BASE+TA_RAM_OFFSET)
#define TA_RAM_SIZE ROUNDDOWN(TZDRAM_SIZE-TA_RAM_OFFSET, CORE_MMU_DEVICE_SIZE)
// SHM is above TA in non-secure DRAM, rigth under secure DRAM
#define TEE_SHMEM_START (TZDRAM_BASE - TEE_SHMEM_SIZE)
#define TEE_SHMEM_SIZE 0x00200000 // 2MB
#endif /* PLATFORM_CONFIG_H */
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