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Removes registration of platform specific secure interrupt handler in
thread_nintr_handler_ptr. Instead a __weak overridable
itr_core_handler() is provided. Platforms which expects to receive
secure interrupts must override the default function. The default
function calls panic() if called.
With this also nintr is removed from struct thread_handlers and
consequently all platforms are updated to stop using that field.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Removes registration of platform specific fast SMC entry function in
thread_fast_smc_handler_ptr. Instead a __weak overridable
tee_entry_fast() is provided. Platforms that need a special
tee_entry_fast() (currently on plat-zynq7k) provides their own
tee_entry_fast() instead which at the end should call __tee_entry_fast()
which does the generic fast call handling.
With this also fast_smc is removed from struct thread_handlers and
consequently all platforms are updated to stop using that field.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Removes registration of platform specific standard SMC entry function in
thread_std_smc_handler_ptr. Instead a __weak overridable tee_entry_std()
is provided. Platforms that need a special tee_entry_std() (currently on
some STM platform) provides their own tee_entry_std() instead which at
the end should call __tee_entry_std() which does the generic standard
call handling.
With this also std_smc is removed from struct thread_handlers and
consequently all platforms are updated to stop using that field.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Fix UART1 base address for zcu102, zc1751_dc1, zc1751_dc2 flavors.
More information provided p226 of UG1085 [1].
Link: [1] https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
Signed-off-by: Michael Grand <michael.grand.mg@gmail.com>
[jf: move URL to a Link: tag]
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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Add flavor 'ultra96' to platform 'zynqmp'.
Redirect TEE console output to UART1.
Signed-off-by: Michael Grand <michael.grand.mg@gmail.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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Device memory registered via register_phys_mem() is currently rounded
up/down to CORE_MMU_PGDIR_SIZE (1 MiB, or 2 MiB for LPAE). This is not
needed and possibly incorrect for SoCs that define I/O memory maps with
regions aligned on a small page (4 KiB), because using a larger
granularity could result in overlaps between secure and non-secure
mappings. This could cause issues depending on the type of memory
firewall used by the SoC and its configuration. In any case, memory
types other than MEM_AREA_IO_{SEC,NSEC} *can* be mapped with small page
granularity using register_phys_mem(), so the situation is a bit
inconsistent.
This commit removes the rounding by default and provides a new macro:
register_phys_mem_pgdir(). Platforms that still need to use PGDIR_SIZE
granularity (typically because it consumes less page table space) need
to replace register_phys_mem() by register_phys_mem_pgdir().
In order to avoid any functional change in platform code, all calls to
register_phys_mem() with device memory are replaced with
register_phys_mem_pgdir(). In addition, CORE_MMU_DEVICE_SIZE is removed
and replaced with CORE_MMU_PGDIR_SIZE since there is no unique mapping
size for device memory anymore.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reported-by: Zeng Tao <prime.zeng@hisilicon.com>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Platforms use the same basic pattern again and again:
ta-targets = ta_arm32
ifeq ($(CFG_ARM64_core),y)
ta-targets += ta_arm64
endif
Let's move this pattern to core/arch/arm/arm.mk, make it the default, and
cleanup the platform configuration files.
Suggested-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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Except for very special cases (such as virtualization), the number of CPU
cores that can enter OP-TEE is a fixed number that depends on the hardware
configuration and should not be configurable at build time.
Therefore, use $(call force,CFG_TEE_CORE_NB_CORE,<value>) to set the
value.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Update platforms d02, rcar, sam, hikey, mediatek, poplar, rpi3, sprd,
zynqmp and marvell.
These platforms no more defines CFG_ configuration directives as
NB_CORE was the last remaining one.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
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TEE_LOAD_ADDR is now local to source files. It is set to CFG_TEE_LOAD_ADDR
value if defined only for the platforms that previously allowed build
to override the value. Few platform did hardcod CFG_TEE_LOAD_ADDR, this
change preserve these configurations.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.
This change renames the CFG_SHMEM_xxx into TEE_SHMEM_xxx so that they
do not mess with the platform configuration directives. Yet, the old
CFG_SHMEM_START/SIZE directives can still be used by platform_config.h
to set TEE_SHMEM_START/SIZE if the platform supports it (i.e plat-stm).
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.
This change renames these macros so that they do not mess with the
platform configuration directives.
Old macro label New macro label
CFG_TA_RAM_START TA_RAM_START
CFG_TA_RAM_SIZE TA_RAM_SIZE
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Almost platform currently define these directives from within the
source code, through platform_config.h. These values do not need to
be configuration directive with the CFG_ prefix.
This change renames these macros so that they do not mess with the
platform configuration directives.
Old macro label New macro label
CFG_TEE_RAM_START TEE_RAM_START
CFG_TEE_RAM_VA_SIZE TEE_RAM_VA_SIZE
CFG_TEE_RAM_PH_SIZE TEE_RAM_PH_SIZE
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Adds one SPDX-License-Identifier line [1] to each source files that
contains license text.
Generated by [2]:
spdxify.py --add-spdx optee_os/
The scancode tool [3] was used to double check the license matching
code in the Python script. All the licenses detected by scancode are
either detected by spdxify.py, or have no SPDX identifier, or are false
matches.
Link: [1] https://spdx.org/licenses/
Link: [2] https://github.com/jforissier/misc/blob/f7b56c8/spdxify.py
Link: [3] https://github.com/nexB/scancode-toolkit
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Joakim Bech <joakim.bech@linaro.org>
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Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU CFG_WITH_VFP=y)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey960 AArch32 {,pager})
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Some platforms set arm32-platform-aflags += -mfpu-neon, which causes
NEON to be selected when building any assembly files. TEE core, user-mode
libraries and TAs are all affected by this setting.
This is most likely incorrect because user-mode libraries do not use
NEON instructions (only some core files do). And, it does not make much
sense to set it by default for TAs either.
So, core_arm32-platform-aflags should be set instead.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Most platform do not need any special linker targets and so most
just link back to the default. Lets just have core.mk use the default
when a platform does not have this file. Also remove this from the
porting guidelines as it is now optional and only needed for advanced
use.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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Most platform do not need any special linker scripting and so most
just link back to the default. Lets just have link.mk use the default
when a platform does not have this file. Also remove this from the
porting guidelines as it is now optional and only needed for advanced
use.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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Initialize the .bss section early from assembler before entering C
code. As a result, the __early_bss qualifier is not needed anymore.
Remove it, as well as the related symbols (__early_bss_start and
__early_bss_end).
This makes the code simpler hence easier to maintain, at the expense
of initialization time, since .bss is cleared before CPU caches are
turned on (and doing it later would mean some C function have been
called already). Here are some performance numbers measured on HiKey.
The "memset" column measures the time it takes to clear .bss in C,
without this patch. The "assembly" column reports the time taken by the
clear_bss loop in this patch. Timings were performed using CNTPCT.
Worst case is a ~1 ms overhead in boot time.
memset(): | assembly:
ms (bytes) | ms (bytes)
--------------+--------------
Aarch64 0.30 (72824) | 0.08 (73528)
Aarch32 0.27 (65016) | 1.24 (65408)
Aarch32/pager 0.03 (11328) | 0.23 (11736)
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (QEMU)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey 32/64)
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (HiKey/pager)
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Create core/arch/arm/cpu/<cpu-name>.mk to store CPU generic configurations
settings. Update supported platforms to rely on the generic CPU support.
Platform shall still specify whether they support or not the NEON
extension.
Cortex-A53 and Cortex-A57 are all ARMv8.0 compliant. For ARMv8 core,
we will use ARMv8-A architecture minor version configuration files.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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HW may or may not support STCLR "WXN" configuration field.
CFG_HWSUPP_MEM_PERM_WXN reflects this state. AArch64 is assumed to
always support this field.
Enable the "WXN" (and UWXN) bits in STCLR upon configuration directive
CFG_CORE_RWDATA_NOEXEC.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
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Macros DEVICEx_TYPE, DEVICEx_PA_BASE and DEVICEx__SIZE used to
help platform to register their address range mapping requirements.
These are now deprecated since platform should use the more flexible
register_phys_mem() macro.
This change removes all occurrences of DEVICEx_TYPE/_PA_BASE/_SIZE
and use the register_phys_mem() instead.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Since most platforms now use the same console_putc() and
console_flush(), move them to core/kernel/console.c. Make them __weak
so that platforms may still provide their own.
The common code expects the platforms to initialize whatever serial
device from console_init() and call register_console().
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
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Removes the now obsolete FS key manager tests. The FS hash tree interface
has taken over much och the FS key manager tasks.
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Currently, the secure interrupts are named as FIQ and the non-secure
interrupts are named as IRQ.
In GICv3 mode, the FIQ and IRQ have different definitions.
* Secure Group 0 interrupts:
Handled by EL3 and triggered by FIQ when running at Secure EL0/1.
* Secure Group 1 interrupts:
Handled by optee_os and triggered by IRQ when running at Secure EL0/1.
* Non-secure Group1 interrupts:
Handled by the rich os and triggered by FIQ when running at Secure
EL0/1.
The "Secure Group 1" interrupts are the "native" interrupts handled by
optee_os. They are same as the "secure" interrupts used in optee_os
for now. But they are triggered by FIQ in GICv2 mode while by IRQ in
GICv3 mode.
The "Secure Group 0" and "Non-secure Group1" interrupts are the
"foreign" interrupts that will cause the exiting of optee_os. (e.g.
switch back to normal world) The "Non-secure Group1" interrupts are
same as the "non-secure"interrupts used in optee_os for now. But they
are triggered by IRQ in GICv2 mode while by FIQ in GICv3 mode.
This patch renames these interrupts to the generic names - "Foreign
interrupts" and "Native interrupts".
For the support of GICv3 mode in the future, we can redefine the macros
of "native interrupt" and "foreign interrupt" to IRQ and FIQ.
Signed-off-by: David Wang <david.wang@arm.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (b2260)
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Adds a CFG_CORE_HEAP_SIZE replacing the defined HEAP_SIZE in each
platform_config.h. Default value is defined in mk/config.mk as 64 kB.
This is larger than most of the previous values at 24 kB or just above.
Platforms with a previous heap size defined larger than 64 kB overrides
the mk/config.mk setting with a $(platform-dir)/conf.mk setting using the
previous value.
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Hikey pager)
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (QEMU v7 pager)
Tested-by: Jens Wiklander <jens.wiklander@linaro.org> (FVP Aarch32 pager)
Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
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Fixes the following error:
$ make -s PLATFORM=stm
core/arch/arm/plat-stm/system_config.mk:20:
*** PLATFORM_FLAVOR=qemu_virt is not supported. Stop.
(one would expect PLATFORM_FLAVOR to default to 'orly2').
This patch does the following:
- Do not set "PLATFORM_FLAVOR ?= qemu_virt" in the main Makefile. The
default value for PLATFORM_FLAVOR has to be defined by each platform in
plat-*/conf.mk.
- Consistent with the above, "PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) := y"
is moved to core/core.mk, after $(platform-dir)/conf.mk has been
included, i.e., where $(PLATFORM_FLAVOR) can be relied upon.
- All definitions of "PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) := y"
are removed from platform files, since it is already taken care of in
core/core.mk.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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..for all platforms by setting
CFG_TEE_CORE_EMBED_INTERNAL_TESTS ?= y
in mk/config.mk.
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Suggested-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Update the main Makefile so that PLATFORM_$(PLATFORM) and
PLATFORM_FLAVOR_$(PLATFORM_FLAVOR) are set to 'y', and add these
variables to the export list for the generation of conf.h.
As a result, the definition of numerical flavor identifiers in the
multiple platform_config.h files is not needed anymore, and we can also
get rid of the PLATFORM_FLAVOR_IS() test macro. Instead, replace all
occurrences of '#if PLATFORM_FLAVOR_IS(foo)' with
'#if defined(PLATFORM_FLAVOR_foo)'.
This makes it possible to test the platform and not only the flavor in
any source file, so drop the manual definition of PLATFORM_hikey.
Finally, remove the definitions of platform_$(PLATFORM) and
platform_flavor_$(PLATFORM_FLAVOR) from core/core.mk since they are not
used.
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: David Brown <david.brown@linaro.org>
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..in console_putc() function.
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
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Commit 1e00aeb97ffa ("core: non-linear mapping of secure world devices")
revealed a bug in the ZynqMP platform that mapped the UART non-secure
but looked up its VA as secure memory, resulting in an exception when
accessing the UART registers.
Fixing this by mapping the UART secure, making the mapping consistent
with the VA lookup.
Fixes: dc57f5a0e8f3 ("Add support for ZynqMP")
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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Add support for Xilinx UltraScale+ Zynq MPSoC.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Reviewed-by: Joakim Bech <joakim.bech@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
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