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Diffstat (limited to 'core/arch/arm/sm/sm_a32.S')
-rw-r--r--core/arch/arm/sm/sm_a32.S11
1 files changed, 0 insertions, 11 deletions
diff --git a/core/arch/arm/sm/sm_a32.S b/core/arch/arm/sm/sm_a32.S
index 83c35feb..81820f63 100644
--- a/core/arch/arm/sm/sm_a32.S
+++ b/core/arch/arm/sm/sm_a32.S
@@ -26,7 +26,6 @@
.endm
FUNC sm_save_unbanked_regs , :
-UNWIND( .fnstart)
UNWIND( .cantunwind)
/* User mode registers has to be saved from system mode */
cps #CPSR_MODE_SYS
@@ -50,7 +49,6 @@ UNWIND( .cantunwind)
#endif
cps #CPSR_MODE_MON
bx lr
-UNWIND( .fnend)
END_FUNC sm_save_unbanked_regs
.macro restore_regs mode
@@ -63,7 +61,6 @@ END_FUNC sm_save_unbanked_regs
/* Restores the mode specific registers */
FUNC sm_restore_unbanked_regs , :
-UNWIND( .fnstart)
UNWIND( .cantunwind)
/* User mode registers has to be saved from system mode */
cps #CPSR_MODE_SYS
@@ -87,7 +84,6 @@ UNWIND( .cantunwind)
#endif
cps #CPSR_MODE_MON
bx lr
-UNWIND( .fnend)
END_FUNC sm_restore_unbanked_regs
/*
@@ -98,7 +94,6 @@ END_FUNC sm_restore_unbanked_regs
* Async abort has to be masked while using stack_tmp.
*/
LOCAL_FUNC sm_smc_entry , :
-UNWIND( .fnstart)
UNWIND( .cantunwind)
srsdb sp!, #CPSR_MODE_MON
push {r0-r7}
@@ -199,7 +194,6 @@ UNWIND( .cantunwind)
.sm_exit:
pop {r0-r7}
rfefd sp!
-UNWIND( .fnend)
END_FUNC sm_smc_entry
/*
@@ -210,7 +204,6 @@ END_FUNC sm_smc_entry
* from FIQ.
*/
LOCAL_FUNC sm_fiq_entry , :
-UNWIND( .fnstart)
UNWIND( .cantunwind)
/* FIQ has a +4 offset for lr compared to preferred return address */
sub lr, lr, #4
@@ -250,12 +243,10 @@ UNWIND( .cantunwind)
add sp, sp, #(SM_CTX_SEC + SM_SEC_CTX_MON_LR)
rfefd sp!
-UNWIND( .fnend)
END_FUNC sm_fiq_entry
.align 5
LOCAL_FUNC sm_vect_table , :
-UNWIND( .fnstart)
UNWIND( .cantunwind)
b . /* Reset */
b . /* Undefined instruction */
@@ -332,12 +323,10 @@ sm_vect_table_bpiall:
/* unhandled exception */
b .
#endif /*!CFG_CORE_WORKAROUND_SPECTRE_BP*/
-UNWIND( .fnend)
END_FUNC sm_vect_table
/* void sm_init(vaddr_t stack_pointer); */
FUNC sm_init , :
-UNWIND( .fnstart)
/* Set monitor stack */
mrs r1, cpsr
cps #CPSR_MODE_MON