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authorEtienne Carriere <etienne.carriere@linaro.org>2018-10-01 16:50:47 +0200
committerJérôme Forissier <jerome.forissier@linaro.org>2018-10-01 17:55:17 +0200
commit09614f8e34cbdd8764453835ae22ee0d4826f49f (patch)
tree640755a8ee187d0c3de60c9376d0cbd7d49aaf12
parent385000b08b0d7ad53b0c13fb1aead0a4e669dd43 (diff)
core: correct memory layout trace
Buffers that end at end of the available address range which may happen on 32bit machine fail have an end address that of computed as 0. This change uses a 64bit address computation to prevent the displayed end address being 0. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
-rw-r--r--core/arch/arm/mm/core_mmu.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/core/arch/arm/mm/core_mmu.c b/core/arch/arm/mm/core_mmu.c
index 634e0c7d..f69069e1 100644
--- a/core/arch/arm/mm/core_mmu.c
+++ b/core/arch/arm/mm/core_mmu.c
@@ -393,8 +393,8 @@ bool core_mmu_nsec_ddr_is_defined(void)
}
#define MSG_MEM_INSTERSECT(pa1, sz1, pa2, sz2) \
- EMSG("[%" PRIxPA " %" PRIxPA "] intersecs [%" PRIxPA " %" PRIxPA "]", \
- pa1, pa1 + sz1, pa2, pa2 + sz2)
+ EMSG("[%" PRIxPA " %" PRIx64 "] intersects [%" PRIxPA " %" PRIx64 "]", \
+ pa1, (uint64_t)pa1 + sz1, pa2, (uint64_t)pa2 + sz2)
#ifdef CFG_SECURE_DATA_PATH
static bool pbuf_is_sdp_mem(paddr_t pbuf, size_t len)
@@ -479,8 +479,8 @@ static void verify_special_mem_areas(struct tee_mmap_region *mem_map,
}
for (mem = start; mem < end; mem++)
- DMSG("%s memory [%" PRIxPA " %" PRIxPA "]",
- area_name, mem->addr, mem->addr + mem->size);
+ DMSG("%s memory [%" PRIxPA " %" PRIx64 "]",
+ area_name, mem->addr, (uint64_t)mem->addr + mem->size);
/* Check memories do not intersect each other */
for (mem = start; mem < end - 1; mem++) {