diff options
| author | Mourad Goumrhar <Mourad.Goumrhar@se.com> | 2020-10-12 17:06:39 +0200 |
|---|---|---|
| committer | Ralph Siemsen <ralph.siemsen@linaro.org> | 2021-11-04 15:13:30 -0400 |
| commit | b2446e41e462624a3e1b3df2e1c2765d1c4eca49 (patch) | |
| tree | ee1c05de54e97c41b55ad38026191ce7e9f7fc98 | |
| parent | 05451e32cd0fccb8dae7436d23de0ccc78059bd9 (diff) | |
plat-rzn1: Add Cortex-M3 startlinaro-rel-2021.08-dunfell.1-rc2linaro-rel-2021.08-dunfell.1-rc1linaro-rel-2021.08-dunfell.1lces2-optee-3.15
Add CFG_BOOT_CM3 flag (default=y) to start the Cortex-M3 after
intialization.
Signed-off-by: Mourad Goumrhar <Mourad.Goumrhar@se.com>
Change-Id: I7d43601ca05d5fdd05f747dec80713b81e673b68
| -rw-r--r-- | core/arch/arm/plat-rzn1/conf.mk | 1 | ||||
| -rw-r--r-- | core/arch/arm/plat-rzn1/main.c | 39 |
2 files changed, 40 insertions, 0 deletions
diff --git a/core/arch/arm/plat-rzn1/conf.mk b/core/arch/arm/plat-rzn1/conf.mk index 453378d1..1a51e482 100644 --- a/core/arch/arm/plat-rzn1/conf.mk +++ b/core/arch/arm/plat-rzn1/conf.mk @@ -13,6 +13,7 @@ $(call force,CFG_WITH_PAGER,n) $(call force,CFG_GIC,y) $(call force,CFG_SM_PLATFORM_HANDLER,y) $(call force,CFG_TA_FLOAT_SUPPORT,n) +$(call force,CFG_BOOT_CM3,y) ta-targets = ta_arm32 diff --git a/core/arch/arm/plat-rzn1/main.c b/core/arch/arm/plat-rzn1/main.c index 192a380b..1f47f264 100644 --- a/core/arch/arm/plat-rzn1/main.c +++ b/core/arch/arm/plat-rzn1/main.c @@ -16,6 +16,15 @@ #include <platform_config.h> #include <rzn1_tz.h> +#define SYSCTRL_PWRCTRL_CM3 (SYSCTRL_BASE + 0x174) +#define SYSCTRL_PWRSTAT_CM3 (SYSCTRL_BASE + 0x178) + +#define SYSCTRL_PWRCTRL_CM3_CLKEN_A BIT(0) +#define SYSCTRL_PWRCTRL_CM3_RSTN_A BIT(1) +#define SYSCTRL_PWRCTRL_CM3_MIREQ_A BIT(2) + +#define SYSCTRL_PWRSTAT_CM3_MIRACK_A BIT(0) + static struct gic_data gic_data; static struct ns16550_data console_data; @@ -72,3 +81,33 @@ static TEE_Result rzn1_tz_init(void) } service_init(rzn1_tz_init); + +#ifdef CFG_BOOT_CM3 +static TEE_Result rzn1_cm3_start(void) +{ + vaddr_t cm3_pwrctrl_reg = 0; + vaddr_t cm3_pwrstat_reg = 0; + + cm3_pwrctrl_reg = core_mmu_get_va(SYSCTRL_PWRCTRL_CM3, MEM_AREA_IO_SEC, + sizeof(uint32_t)); + cm3_pwrstat_reg = core_mmu_get_va(SYSCTRL_PWRSTAT_CM3, MEM_AREA_IO_SEC, + sizeof(uint32_t)); + + IMSG("Starting Cortex-M3"); + // Master Idle Request to the interconnect for CM3. + io_clrbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_MIREQ_A); + + // Wait for Master Idle Request Acknowledge for CM3 + while (io_read32(cm3_pwrstat_reg) & SYSCTRL_PWRSTAT_CM3_MIRACK_A) { + // wait + } + + // Clock Enable for CM3_HCLK & Active low Reset to CM3 + io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_CLKEN_A); + io_setbits32(cm3_pwrctrl_reg, SYSCTRL_PWRCTRL_CM3_RSTN_A); + + return TEE_SUCCESS; +} + +service_init(rzn1_cm3_start); +#endif |